Information

FTMx_SYNCONF field descriptions (continued)
Field Description
0 CNTIN register is updated with its buffer value at all rising edges of system clock.
1 CNTIN register is updated with its buffer value by the PWM synchronization.
1
Reserved
This read-only field is reserved and always has the value zero.
0
HWTRIGMODE
Hardware Trigger Mode
0 FTM clears the TRIGj bit when the hardware trigger j is detected.
1 FTM does not clear the TRIGj bit when the hardware trigger j is detected.
37.3.25 FTM Inverting Control (FTMx_INVCTRL)
This register controls controls when the channel (n) output becomes the channel (n+1)
output, and channel (n+1) output becomes the channel (n) output. Each INVmEN bit
enables the inverting operation for the corresponding pair channels m.
This register has a write buffer. The INVmEN bit is updated by the INVCTRL register
synchronization.
Addresses: FTM0_INVCTRL is 4003_8000h base + 90h offset = 4003_8090h
FTM1_INVCTRL is 4003_9000h base + 90h offset = 4003_9090h
FTM2_INVCTRL is 400B_8000h base + 90h offset = 400B_8090h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
INV3EN INV2EN INV1EN INV0EN
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FTMx_INVCTRL field descriptions
Field Description
31–4
Reserved
This read-only field is reserved and always has the value zero.
3
INV3EN
Pair Channels 3 Inverting Enable
0 Inverting is disabled.
1 Inverting is enabled.
2
INV2EN
Pair Channels 2 Inverting Enable
0 Inverting is disabled.
1 Inverting is enabled.
1
INV1EN
Pair Channels 1 Inverting Enable
Table continues on the next page...
Memory Map and Register Definition
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
930 Freescale Semiconductor, Inc.