Information

When a selected edge occurs on the channel input, the current value of the FTM counter
is captured into the CnV register, at the same time the CHnF bit is set and the channel
interrupt is generated if enabled by CHnIE = 1 (see the following figure).
When a channel is configured for input capture, the FTMxCHn pin is an edge-sensitive
input. ELSnB:ELSnA control bits determine which edge, falling or rising, triggers input-
capture event. Note that the maximum frequency for the channel input signal to be
detected correctly is system clock divided by 4, which is required to meet Nyquist criteria
for signal sampling.
Writes to the CnV register is ignored in input capture mode.
While in BDM, the input capture function works as configured. When a selected edge
event occurs, the FTM counter value (which is frozen because of BDM) is captured into
the CnV register and the CHnF bit is set.
channel (n) input
synchronizer
1
is filter
enabled?
edge
detector
was falling
edge selected?
was rising
edge selected?
rising edge
falling edge
0
1
1
0
0 0
CnV
FTM counter
D Q
CLK
D Q
CLK
system clock
channel (n) interrupt
CHnIE
CHnF
Filter*
0
* Filtering function is only available in the inputs of channel 0, 1, 2, and 3
Figure 37-175. Input Capture Mode
If the channel input does not have a filter enabled, then the input signal is always delayed
3 rising edges of the system clock (two rising edges to the synchronizer plus one more
rising edge to the edge detector). In other words, the CHnF bit is set on the third rising
edge of the system clock after a valid edge occurs on the channel input.
Note
It is expected that the input capture mode be used only with
CNTIN = 0x0000.
37.4.4.1 Filter for Input Capture Mode
The filter function is only available on channels 0, 1, 2, and 3.
Functional Description
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
942 Freescale Semiconductor, Inc.