Information

channel (n) output
CHnF bit
TOF bit
CNT
MOD = 0x0005
CnV = 0x0003
counter
overflow
channel (n)
match
counter
overflow
channel (n)
match
counter
overflow
...
0
1
2
3 4 5
0
1
2
3
4
5
0
1
...
previous value
previous value
Figure 37-180. Example of the Output Compare Mode when the Match Sets the Channel
Output
It is possible to use the output compare mode with (ELSnB:ELSnA = 0:0). In this case,
when the counter reaches the value in the CnV register, the CHnF bit is set and the
channel (n) interrupt is generated (if CHnIE = 1), however the channel (n) output is not
modified and controlled by FTM.
Note
It is expected that the output compare mode be used only with
CNTIN = 0x0000.
37.4.6 Edge-Aligned PWM (EPWM) Mode
The edge-aligned mode is selected when (QUADEN = 0), (DECAPEN = 0), (COMBINE
= 0), (CPWMS = 0), and (MSnB = 1).
The EPWM period is determined by (MOD − CNTIN + 0x0001) and the pulse width
(duty cycle) is determined by (CnV − CNTIN).
The CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1) at the
channel (n) match (FTM counter = CnV), that is, at the end of the pulse width.
This type of PWM signal is called edge-aligned because the leading edges of all PWM
signals are aligned with the beginning of the period, which is the same for all channels
within an FTM.
period
counter overflow counter overflow counter overflow
channel (n) output
channel (n) match channel (n) match
channel (n) match
pulse
width
Figure 37-181. EPWM Period and Pulse Width with ELSnB:ELSnA = 1:0
Chapter 37 FlexTimer (FTM)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 945