Information

If (CLKS[1:0] ≠ 0:0 and FTMEN = 0), then MOD register is updated according to the
CPWMS bit, that is:
• If the selected mode is not CPWM then MOD register is updated after MOD register
was written and the FTM counter changes from MOD to CNTIN. If the FTM counter
is at free-running counter mode then this update occurs when the FTM counter
changes from 0xFFFF to 0x0000.
• If the selected mode is CPWM then MOD register is updated after MOD register was
written and the FTM counter changes from MOD to (MOD – 0x0001).
If (CLKS[1:0] ≠ 0:0 and FTMEN = 1) then MOD register is updated by the MOD register
synchronization (MOD Register Synchronization).
37.4.10.3 CnV Register Update
If (CLKS[1:0] = 0:0) then CnV register is updated when CnV register is written
(independent of FTMEN bit).
If (CLKS[1:0] ≠ 0:0 and FTMEN = 0), then CnV register is updated according to the
selected mode, that is:
• If the selected mode is output compare then CnV register is updated on the next FTM
counter change (end of the prescaler counting) after CnV register was written.
• If the selected mode is EPWM then CnV register is updated after CnV register was
written and the FTM counter changes from MOD to CNTIN. If the FTM counter is at
free-running counter mode then this update occurs when the FTM counter changes
from 0xFFFF to 0x0000.
• If the selected mode is CPWM then CnV register is updated after CnV register was
written and the FTM counter changes from MOD to (MOD – 0x0001).
If (CLKS[1:0] ≠ 0:0 and FTMEN = 1) then CnV register is updated according to the
selected mode, that is:.
Functional Description
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
958 Freescale Semiconductor, Inc.