Information

write 1 to TRIG0 bit
system clock
synchronized trigger_0
trigger 0 event
Note
TRIG0 bit
trigger_0 input
by system clock
All hardware trigger inputs have the same behavior.
Figure 37-205. Hardware Trigger Event with HWTRIGMODE = 0
If HWTRIGMODE = 1 then the TRIGn bit is only cleared when 0 is written to it.
NOTE
It is expected that the HWTRIGMODE bit be 1 only with
enhanced PWM synchronization (SYNCMODE = 1).
37.4.11.2 Software Trigger
A software trigger event occurs when 1 is written to the SYNC[SWSYNC] bit. The
SWSYNC bit is cleared when 0 is written to it or when the PWM synchronization
(initiated by the software event) is completed.
If a new software trigger event occurs (write 1 to SWSYNC bit) together with the end of
the previous synchronization (also initiated by the software trigger event) then this new
synchronization is started and SWSYNC bit remains equal to 1.
If SYNCMODE = 0 then the SWSYNC bit is also cleared by FTM according to
PWMSYNC and REINIT bits. In this case if (PWMSYNC = 1) or (PWMSYNC = 0 and
REINIT = 0) then SWSYNC bit is cleared at the next selected loading point (Boundary
Cycle and Loading Points) after that the software trigger event occurred (see the
following figure). If (PWMSYNC = 0) and (REINIT = 1) then SWSYNC bit is cleared
when the software trigger event occurs.
If SYNCMODE = 1 then the SWSYNC bit is also cleared by FTM according to the
SWRSTCNT bit. If SWRSTCNT = 0 then SWSYNC bit is cleared at the next selected
loading point after that the software trigger event occurred (see the following figure). If
SWRSTCNT = 1 then SWSYNC bit is cleared when the software trigger event occurs.
Functional Description
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
960 Freescale Semiconductor, Inc.