Information

Register
access
Flash memory
controller
Transfers
Memory protection
unit
Peripheral bus
controller 0
Transfers
Flash memory
Crossbar switch
Figure 3-23. Flash memory controller configuration
Table 3-36. Reference links to related information
Topic Related module Reference
Full description Flash memory
controller
Flash memory controller
System memory map System memory map
Clocking Clock Distribution
Transfers Flash memory Flash memory
Transfers MPU MPU
Transfers Crossbar switch Crossbar Switch
Register access Peripheral bridge Peripheral bridge
3.5.2.1 Number of masters
The Flash Memory Controller supports up to eight crossbar switch masters. However,
this device has a different number of crossbar switch masters. See Crossbar Switch
Configuration for details on the master port assignments.
3.5.2.2 Program Flash Swap
On devices that contain program flash memory only, the program flash memory blocks
may swap their base addresses.
While not using swap:
• FMC_PFB0CR controls the lower code addresses (block 0)
• FMC_PFB1CR controls the upper code addresses (block 1)
If swap is used, the opposite is true:
Memories and Memory Interfaces
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
98 Freescale Semiconductor, Inc.