Information

fault input n*
system clock
* where n = 3, 2, 1, 0
synchronizer
fault input n* value
FAULTFn*
0000)
and (FFLTRnEN*)
0
1
rising edge
detector
fault input
polarity
control
Fault filter
(5-bit counter)
CLK
CLK
D D
Q
Q
FLTnPOL
(FFVAL[3:0]
Figure 37-233. Fault Input n Control Block Diagram
If the fault control and fault input n are enabled and a rising edge at the fault input n
signal is detected, then the FAULTFn bit is set. The FAULTF bit is the logic OR of
FAULTFn[3:0] bits (see the following figure).
fault interrupt
FAULTIE
FAULTIN
fault input 0 value
fault input 1 value
fault input 2 value
fault input 3 value
FAULTF
FAULTF0
FAULTF1
FAULTF2
FAULTF3
Figure 37-234. FAULTF and FAULTIN Bits and Fault Interrupt
If the fault control is enabled (FAULTM[1:0] ≠ 0:0), a fault condition has occurred
(rising edge at the logic OR of the enabled fault inputs) and (FAULTEN = 1), then
channels (n) and (n+1) output are forced to their safe value (the channel (n) output is
forced to the value of POL(n) and the channel (n+1) is forced to the value of POL(n+1)).
The fault interrupt is generated when (FAULTF = 1) and (FAULTIE = 1). This interrupt
request remains set until:
• Software clears the FAULTF bit (by reading FAULTF bit as 1 and writing 0 to it)
• Software clears the FAULTIE bit
• A reset occurs
Note
It is expected that the fault control be used only in combine
mode.
Chapter 37 FlexTimer (FTM)
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 983