Information

• FMC_PFB0CR controls the upper code addresses (now in block 0)
• FMC_PFB1CR controls the lower code addresses (now in block 1)
3.5.3 SRAM Configuration
This section summarizes how the module has been configured in the chip.
SRAM upper
Transfers
SRAM controller
Cortex-M4
core
MPU
Crossbar
switch
SRAM lower
MPU
Figure 3-24. SRAM configuration
Table 3-37. Reference links to related information
Topic Related module Reference
Full description SRAM SRAM
System memory map System memory map
Clocking Clock Distribution
Transfers SRAM controller SRAM controller
ARM Cortex-M4 core ARM Cortex-M4 core
Memory protection unit Memory protection unit
3.5.3.1 SRAM sizes
This device contains SRAM tightly coupled to the ARM Cortex-M4 core. The amount of
SRAM for the devices covered in this document is shown in the following table.
Device SRAM (KB)
MK10DX128ZVLQ10 32
MK10DX128ZVMD10 32
MK10DX256ZVLQ10 64
MK10DX256ZVMD10 64
MK10DN512ZVLQ10 128
MK10DN512ZVMD10 128
Chapter 3 Chip Configuration
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 99