Information

edge is detected, that is, the edge selected by ELS(n)B:ELS(n)A bits. The CH(n+1)F bit
is set when the second rising edge is detected, that is, the edge selected by ELS(n
+1)B:ELS(n+1)A bits. The CH(n+1)F bit indicates when two edges of the period were
captured and the C(n)V and C(n+1)V registers are ready for reading.
channel (n) input
(after the filter
DECAPEN bit
C(n+1)V
FTM counter
clear CH(n+1)F
2
1
2
3
channel input)
DECAP bit
set DECAPEN
set DECAP
5
6
7
8
10
3
4
6
5
Note
- The commands set DECAPEN, set DECAP, clear CH(n)F, and clear CH(n+1)F are made by the user.
4
9
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9
10
7
15
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28
15
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21
C(n)V
CH(n+1)F bit
CH(n)F bit
clear CH(n)F
1
8
12
22
24
11
19
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23
25 27
23
20
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17
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1614
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Figure 37-248. Dual Edge Capture – Continuous Mode to Measure of the Period Between
Two Consecutive Rising Edges
37.4.24.5 Read Coherency Mechanism
The dual edge capture mode implements a read coherency mechanism between the FTM
counter value captured in C(n)V and C(n+1)V registers. The read coherency mechanism
is illustrated in the following figure. In this example, the channels (n) and (n+1) are in
dual edge capture – continuous mode for positive polarity pulse width measurement.
Thus, the channel (n) is configured to capture the FTM counter value when there is a
rising edge at channel (n) input signal, and channel (n+1) to capture the FTM counter
value when there is a falling edge at channel (n) input signal.
Functional Description
K10 Sub-Family Reference Manual, Rev. 6, Nov 2011
998 Freescale Semiconductor, Inc.