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K10P100M72SF1

K10 Sub-Family

Supports: MK10DX128VLL7,

MK10DX256VLL7, MK10DX64VMC7,

MK10DX128VMC7, MK10DX256VMC7

Features

•

Operating Characteristics

–

Voltage range: 1.71 to 3.6 V

– Flash write voltage range: 1.71 to 3.6 V

– Temperature range (ambient): -40 to 105°C

•

Clocks

– 3 to 32 MHz crystal oscillator

– 32 kHz crystal oscillator

– Multi-purpose clock generator

•

System peripherals

– Multiple low-power modes to provide power

optimization based on application requirements

– 16-channel DMA controller, supporting up to 63

request sources

– External watchdog monitor

– Software watchdog

– Low-leakage wakeup unit

•

Security and integrity modules

– Hardware CRC module to support fast cyclic

redundancy checks

– 128-bit unique identification (ID) number per chip

•

Human-machine interface

– Low-power hardware touch sensor interface (TSI)

– General-purpose input/output

•

Analog modules

– Two 16-bit SAR ADCs

– Programmable gain amplifier (PGA) (up to x64)

integrated into each ADC

– 12-bit DAC

– Three analog comparators (CMP) containing a 6-bit

DAC and programmable reference input

– Voltage reference

•

Timers

– Programmable delay block

– Eight-channel motor control/general purpose/PWM

timer

– Two 2-channel quadrature decoder/general purpose

timers

– Periodic interrupt timers

– 16-bit low-power timer

– Carrier modulator transmitter

– Real-time clock

•

Communication interfaces

– Controller Area Network (CAN) module

– Two SPI modules

– Two I2C modules

– Five UART modules

– I2S module

Freescale Semiconductor

Document Number: K10P100M72SF1

Data Sheet: Technical Data

Rev. 3, 11/2012

Freescale reserves the right to change the detail specifications as may be

required to permit improvements in the design of its products.

Summary of content (72 pages)

PAGE 1
Freescale Semiconductor Data Sheet: Technical Data Document Number: K10P100M72SF1 Rev. 3, 11/2012 K10P100M72SF1 K10 Sub-Family Supports: MK10DX128VLL7, MK10DX256VLL7, MK10DX64VMC7, MK10DX128VMC7, MK10DX256VMC7 Features • Operating Characteristics – Voltage range: 1.71 to 3.6 V – Flash write voltage range: 1.71 to 3.
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Table of Contents 1 Ordering parts...........................................................................3 5.4.2 Thermal attributes.................................................21 1.1 Determining valid orderable parts......................................3 6 Peripheral operating requirements and behaviors....................22 2 Part identification......................................................................3 6.1 Core modules.............................................................
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Ordering parts 1 Ordering parts 1.1 Determining valid orderable parts Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to www.freescale.com and perform a part number search for the following device numbers: PK10 and MK10 . 2 Part identification 2.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 2.
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Terminology and guidelines Field Description Values FFF Program flash memory size • • • • • • 32 = 32 KB 64 = 64 KB 128 = 128 KB 256 = 256 KB 512 = 512 KB 1M0 = 1 MB R Silicon revision • Z = Initial • (Blank) = Main • A = Revision after main T Temperature range (°C) • V = –40 to 105 • C = –40 to 85 PP Package identifier • • • • • • • • • • • FM = 32 QFN (5 mm x 5 mm) FT = 48 QFN (7 mm x 7 mm) LF = 48 LQFP (7 mm x 7 mm) LH = 64 LQFP (10 mm x 10 mm) MP = 64 MAPBGA (5 mm x 5 mm) LK = 80 LQFP (1
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Terminology and guidelines 3.1.1 Example This is an example of an operating requirement, which you must meet for the accompanying operating behaviors to be guaranteed: Symbol VDD Description 1.0 V core supply voltage Min. 0.9 Max. 1.1 Unit V 3.2 Definition: Operating behavior An operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. 3.2.
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Terminology and guidelines 3.4 Definition: Rating A rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: • Operating ratings apply during operation of the chip. • Handling ratings apply when the chip is not powered. 3.4.1 Example This is an example of an operating rating: Symbol VDD Description 1.0 V core supply voltage Min. –0.3 Max. 1.2 Unit V 3.
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Terminology and guidelines 3.6 Relationship between ratings and operating requirements e Op ing rat r ( ng ati in. t (m ) n. mi rat e Op ing ) t (m e ir qu re n me ing rat e Op ax .) e ir qu re n me ing rat e Op ng ati ax (m .
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Terminology and guidelines 3.8.1 Example 1 This is an example of an operating behavior that includes a typical value: Symbol Description IWP Digital I/O weak pullup/pulldown current Min. 10 Typ. 70 Max. 130 Unit µA 3.8.2 Example 2 This is an example of a chart that shows typical values for various voltage and temperature conditions: 5000 4500 4000 TJ IDD_STOP (μA) 3500 150 °C 3000 105 °C 2500 25 °C 2000 –40 °C 1500 1000 500 0 0.90 0.95 1.00 1.05 1.10 VDD (V) 3.
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Ratings 4 Ratings 4.1 Thermal handling ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 4.
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General Symbol IDD Description Max. Unit — 185 mA VDIO Digital input voltage (except RESET, EXTAL, and XTAL) –0.3 5.5 V VAIO Analog1, RESET, EXTAL, and XTAL input voltage –0.3 VDD + 0.3 V Maximum current single pin limit (applies to all digital pins) –25 25 mA VDD – 0.3 VDD + 0.3 V –0.3 3.8 V ID Digital supply current Min. VDDA Analog supply voltage VBAT RTC battery supply voltage 1.
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General 5.2.1 Voltage and current operating requirements Table 1. Voltage and current operating requirements Symbol Description Min. Max. Unit VDD Supply voltage 1.71 3.6 V VDDA Analog supply voltage 1.71 3.6 V VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V 1.71 3.6 V • 2.7 V ≤ VDD ≤ 3.6 V 0.7 × VDD — V • 1.7 V ≤ VDD ≤ 2.7 V 0.75 × VDD — V • 2.7 V ≤ VDD ≤ 3.6 V — 0.35 × VDD V • 1.7 V ≤ VDD ≤ 2.7 V — 0.
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General 5.2.2 LVD and POR operating requirements Table 2. VDD supply LVD and POR operating requirements Symbol Description Min. Typ. Max. Unit VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V VLVDH Falling low-voltage detect threshold — high range (LVDV=01) 2.48 2.56 2.64 V Low-voltage warning thresholds — high range 1 VLVW1H • Level 1 falling (LVWV=00) 2.62 2.70 2.78 V VLVW2H • Level 2 falling (LVWV=01) 2.72 2.80 2.88 V VLVW3H • Level 3 falling (LVWV=10) 2.82 2.90 2.
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General 5.2.3 Voltage and current operating behaviors Table 4. Voltage and current operating behaviors Symbol VOH Description Min. Max. Unit • 2.7 V ≤ VDD ≤ 3.6 V, IOH = -9mA VDD – 0.5 — V • 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA VDD – 0.5 — V • 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA VDD – 0.5 — V • 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA VDD – 0.5 — V — 100 mA • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 9mA — 0.5 V • 1.71 V ≤ VDD ≤ 2.7 V, IOL = 3mA — 0.5 V • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2mA — 0.5 V • 1.
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General Table 5. Power mode transition operating behaviors Symbol tPOR Description After a POR event, amount of time from the point VDD reaches 1.71 V to execution of the first instruction across the operating temperature range of the chip. • VLLS1 → RUN • VLLS2 → RUN • VLLS3 → RUN • LLS → RUN • VLPS → RUN • STOP → RUN Min. Max. Unit Notes — 300 μs 1 — 112 μs — 74 μs — 73 μs — 5.9 μs — 5.8 μs — 4.2 μs 1. Normal boot (FTFL_OPT[LPBOOT]=1) 5.2.
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General Table 6. Power consumption operating behaviors (continued) Symbol Description IDD_VLPW Very-low-power wait mode current at 3.0 V — all peripheral clocks disabled IDD_STOP Stop mode current at 3.0 V IDD_VLPS IDD_LLS IDD_VLLS3 IDD_VLLS2 IDD_VLLS1 IDD_VBAT Min. Typ. Max. Unit Notes — 0.61 — mA 8 • @ –40 to 25°C — 0.35 0.567 mA • @ 70°C — 0.384 0.793 mA • @ 105°C — 0.628 1.2 mA • @ –40 to 25°C — 5.9 32.7 μA • @ 70°C — 26.1 59.8 μA • @ 105°C — 98.
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General Table 6. Power consumption operating behaviors (continued) Symbol Description Min. IDD_VBAT Average current when CPU is not accessing RTC registers Typ. Max. Unit Notes 10 • @ 1.8V • @ –40 to 25°C • @ 70°C • @ 105°C — 0.57 0.67 μA — 0.90 1.2 μA — 2.4 3.5 μA — 0.67 0.94 μA — 1.0 1.4 μA — 2.7 3.9 μA • @ 3.0V • @ –40 to 25°C • @ 70°C • @ 105°C 1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.
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General Figure 2. Run mode supply current vs. core frequency K10 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc.
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General Figure 3. VLPR mode supply current vs. core frequency 5.2.6 Designing with radiated emissions in mind To find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. Go to www.freescale.com. 2. Perform a keyword search for “EMC design.” 5.2.7 Capacitance attributes Table 7. Capacitance attributes Symbol Description Min. Max.
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General 5.3 Switching specifications 5.3.1 Device clock specifications Table 8. Device clock specifications Symbol Description Min. Max. Unit Notes Normal run mode fSYS System and core clock — 72 MHz fBUS Bus clock — 50 MHz FlexBus clock — 50 MHz fFLASH Flash clock — 25 MHz fLPTMR LPTMR clock — 25 MHz FB_CLK VLPR mode1 fSYS System and core clock — 4 MHz fBUS Bus clock — 4 MHz FB_CLK FlexBus clock — 4 MHz fFLASH Flash clock — 0.
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General Table 9. General switching specifications (continued) Symbol Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter disabled, analog filter disabled) — Asynchronous path 16 — ns 3 External reset pulse width (digital glitch filter disabled) 100 — ns 3 2 — Bus clock cycles Mode select (EZP_CS) hold time after reset deassertion Port rise and fall time (high drive strength) 4 • Slew disabled • 1.71 ≤ VDD ≤ 2.7V — 12 ns • 2.7 ≤ VDD ≤ 3.
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General 5.4.2 Thermal attributes Board type Symbol Description Single-layer (1s) RθJA Four-layer (2s2p) 100 LQFP Unit Notes Thermal 74 resistance, junction to ambient (natural convection) 52 °C/W 1, 2 RθJA Thermal 42 resistance, junction to ambient (natural convection) 40 °C/W 1, 3 Single-layer (1s) RθJMA Thermal 62 resistance, junction to ambient (200 ft./ min. air speed) 42 °C/W 1,3 Four-layer (2s2p) RθJMA Thermal 38 resistance, junction to ambient (200 ft./ min.
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Peripheral operating requirements and behaviors 5. 6. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate temperature used for the case temperature. The value includes the thermal resistance of the interface material between the top of the package and the cold plate. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions—Natural Convection (Still Air).
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Peripheral operating requirements and behaviors 6.1.2 JTAG electricals Table 12. JTAG limited voltage range electricals Symbol J1 Description Min. Max. Unit Operating voltage 2.7 3.
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Peripheral operating requirements and behaviors Table 13. JTAG full voltage range electricals (continued) Symbol Description Min. Max. Unit J5 Boundary scan input data setup time to TCLK rise 20 — ns J6 Boundary scan input data hold time after TCLK rise 0 — ns J7 TCLK low to boundary scan output data valid — 25 ns J8 TCLK low to boundary scan output high-Z — 25 ns J9 TMS, TDI input data setup time to TCLK rise 8 — ns J10 TMS, TDI input data hold time after TCLK rise 1.
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Peripheral operating requirements and behaviors TCLK J9 TDI/TMS J10 Input data valid J11 TDO Output data valid J12 TDO J11 TDO Output data valid Figure 8. Test Access Port timing TCLK J14 J13 TRST Figure 9. TRST timing 6.2 System modules There are no specifications necessary for the device's system modules. 6.3 Clock modules K10 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc.
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Peripheral operating requirements and behaviors 6.3.1 MCG specifications Table 14. MCG specifications Symbol Description Min. Typ. Max. Unit — 32.768 — kHz 31.25 — 39.0625 kHz Δfdco_res_t Resolution of trimmed average DCO output frequency at fixed voltage and temperature — using SCTRIM and SCFTRIM — ± 0.3 ± 0.6 %fdco 1 Δfdco_res_t Resolution of trimmed average DCO output frequency at fixed voltage and temperature — using SCTRIM only — ± 0.2 ± 0.
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Peripheral operating requirements and behaviors Table 14. MCG specifications (continued) Symbol Jcyc_fll Description FLL period jitter • fVCO = 48 MHz • fVCO = 98 MHz tfll_acquire FLL target frequency acquisition time Min. Typ. Max. Unit — 180 — — 150 — — — 1 ms 48.0 — 100 MHz — 1060 — µA — 600 — µA 2.0 — 4.
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Peripheral operating requirements and behaviors 6.3.2.1 Oscillator DC electrical specifications Table 15. Oscillator DC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 — 3.6 V IDDOSC IDDOSC Supply current — low-power mode (HGO=0) Notes 1 • 32 kHz — 500 — nA • 4 MHz — 200 — μA • 8 MHz (RANGE=01) — 300 — μA • 16 MHz — 950 — μA • 24 MHz — 1.2 — mA • 32 MHz — 1.
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Peripheral operating requirements and behaviors Table 15. Oscillator DC electrical specifications (continued) Symbol Vpp5 1. 2. 3. 4. 5. Description Min. Typ. Max. Unit Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, low-power mode (HGO=0) — 0.6 — V Peak-to-peak amplitude of oscillation (oscillator mode) — low-frequency, high-gain mode (HGO=1) — VDD — V Peak-to-peak amplitude of oscillation (oscillator mode) — high-frequency, low-power mode (HGO=0) — 0.
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Peripheral operating requirements and behaviors 4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register being set. NOTE The 32 kHz oscillator works in low power mode by default and cannot be moved into high power/gain mode. 6.3.3 32 kHz Oscillator Electrical Characteristics This section describes the module electrical characteristics. 6.3.3.1 32 kHz oscillator DC electrical specifications Table 17.
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Peripheral operating requirements and behaviors 6.4.1.1 Flash timing specifications — program and erase The following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. Table 19. NVM program/erase timing specifications Symbol Description Min. Typ. Max. Unit thvpgm4 thversscr Notes Longword Program high-voltage time — 7.
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Peripheral operating requirements and behaviors Table 20. Flash command timing specifications (continued) Symbol tvfykey Description Verify Backdoor Access Key execution time Min. Typ. Max.
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Peripheral operating requirements and behaviors 6.4.1.3 Flash high voltage current behaviors Table 21. Flash high voltage current behaviors Symbol Description IDD_PGM IDD_ERS 6.4.1.4 Symbol Min. Typ. Max. Unit Average current adder during high voltage flash programming operation — 2.5 6.0 mA Average current adder during high voltage flash erase operation — 1.5 4.0 mA Reliability specifications Table 22. NVM reliability specifications Description Min. Typ.1 Max.
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Peripheral operating requirements and behaviors The bytes not assigned to data flash via the FlexNVM partition code are used by the flash memory module to obtain an effective endurance increase for the EEPROM data. The built-in EEPROM record management system raises the number of program/erase cycles that can be attained prior to device wear-out by cycling the EEPROM data through a larger EEPROM NVM storage space.
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Peripheral operating requirements and behaviors Figure 10. EEPROM backup writes to FlexRAM 6.4.2 EzPort Switching Specifications Table 23. EzPort switching specifications Num Description Min. Max. Unit Operating voltage 1.71 3.
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Peripheral operating requirements and behaviors EZP_CK EP3 EP2 EP4 EZP_CS EP9 EP7 EP8 EZP_Q (output) EP5 EP6 EZP_D (input) Figure 11. EzPort Timing Diagram 6.4.3 Flexbus Switching Specifications All processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be the same as the internal system bus frequency or an integer divider of that frequency.
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Peripheral operating requirements and behaviors 2. Specification is valid for all FB_AD[31:0] and FB_TA. Table 25. Flexbus full voltage range switching specifications Num Description Min. Max. Unit Operating voltage 1.71 3.6 V Frequency of operation Notes — FB_CLK MHz 1/FB_CLK — ns Address, data, and control output valid — 13.5 ns 1 FB3 Address, data, and control output hold 0 — ns 1 FB4 Data and FB_TA input setup 13.7 — ns 2 FB5 Data and FB_TA input hold 0.
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Peripheral operating requirements and behaviors FB1 FB_CLK FB3 FB5 FB_A[Y] Address FB4 FB2 FB_D[X] Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB4 FB_BEn FB5 AA=1 FB_TA FB_TSIZ[1:0] AA=0 TSIZ Figure 12. FlexBus read timing diagram K10 Sub-Family Data Sheet, Rev. 3, 11/2012. 38 Freescale Semiconductor, Inc.
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Peripheral operating requirements and behaviors FB1 FB_CLK FB2 FB3 FB_A[Y] FB_D[X] Address Address Data FB_RW FB_TS FB_ALE AA=1 FB_CSn AA=0 FB_OEn FB4 FB_BEn FB5 AA=1 FB_TA FB_TSIZ[1:0] AA=0 TSIZ Figure 13. FlexBus write timing diagram 6.5 Security and integrity modules There are no specifications necessary for the device's security and integrity modules. 6.6 Analog K10 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc.
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Peripheral operating requirements and behaviors 6.6.1 ADC electrical specifications The 16-bit accuracy specifications listed in Table 26 and Table 27 are achievable on the differential pins ADCx_DP0, ADCx_DM0. The ADCx_DP2 and ADCx_DM2 ADC inputs are connected to the PGA outputs and are not direct device pins. Accuracy specifications for these pins are defined in Table 28 and Table 29. All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 6.6.1.
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Peripheral operating requirements and behaviors Table 26. 16-bit ADC operating conditions (continued) Symbol Crate Description Conditions ADC conversion rate 16-bit mode Min. Typ.1 Max. Unit Notes 5 No ADC hardware averaging 37.037 — 461.467 Ksps Continuous conversions enabled, subsequent conversion time 1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2.
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Peripheral operating requirements and behaviors Table 27. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol fADACK Description ADC asynchronous clock source Sample Time TUE DNL INL EFS Conditions1 Min. Typ.2 Max. Unit Notes • ADLPC = 1, ADHSC = 0 1.2 2.4 3.9 MHz • ADLPC = 1, ADHSC = 1 2.4 4.0 6.1 MHz tADACK = 1/ fADACK • ADLPC = 0, ADHSC = 0 3.0 5.2 7.3 MHz • ADLPC = 0, ADHSC = 1 4.4 6.2 9.
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Peripheral operating requirements and behaviors Table 27. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Symbol Description EIL Input leakage error Conditions1 Min. Typ.2 Max. IIn × RAS Unit Notes mV IIn = leakage current (refer to the MCU's voltage and current operating ratings) VTEMP25 Temp sensor slope Across the full temperature range of the device — 1.715 — mV/°C Temp sensor voltage 25 °C — 719 — mV 1.
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Peripheral operating requirements and behaviors Figure 16. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode 6.6.1.3 16-bit ADC with PGA operating conditions Table 28. 16-bit ADC with PGA operating conditions Symbol Description Conditions Min. Typ.1 Max. Unit VDDA Supply voltage Absolute 1.71 — 3.
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Peripheral operating requirements and behaviors Table 28. 16-bit ADC with PGA operating conditions (continued) Symbol Crate Description Conditions ADC conversion rate ≤ 13 bit modes Min. Typ.1 Max. Unit Notes 18.484 — 450 Ksps 7 37.037 — 250 Ksps 8 No ADC hardware averaging Continuous conversions enabled Peripheral clock = 50 MHz 16 bit modes No ADC hardware averaging Continuous conversions enabled Peripheral clock = 50 MHz 1. Typical values assume VDDA = 3.
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Peripheral operating requirements and behaviors Table 29. 16-bit ADC with PGA characteristics (continued) Symbol G BW Description Gain4 Input signal bandwidth PSRR Power supply rejection ratio CMRR Common mode rejection ratio Min. Typ.1 Max. • PGAG=0 0.95 1 1.05 • PGAG=1 1.9 2 2.1 • PGAG=2 3.8 4 4.2 • PGAG=3 7.6 8 8.4 • PGAG=4 15.2 16 16.6 • PGAG=5 30.0 31.6 33.2 • PGAG=6 58.8 63.3 67.
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Peripheral operating requirements and behaviors Table 29. 16-bit ADC with PGA characteristics (continued) Symbol Description SFDR Spurious free dynamic range Effective number of bits ENOB SINAD Signal-to-noise plus distortion ratio Min. Typ.1 Max. Unit Notes • Gain=1 85 105 — dB • Gain=64 53 88 — dB 16-bit differential mode, Average=32, fin=100Hz • Gain=1, Average=4 11.6 13.4 — bits • Gain=64, Average=4 7.2 9.6 — bits • Gain=1, Average=32 12.8 14.
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Peripheral operating requirements and behaviors Table 30. Comparator and 6-bit DAC electrical specifications (continued) Symbol Description Min. Typ. Max. Unit VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.
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Peripheral operating requirements and behaviors 0.18 0.16 0.14 CMP P Hystereris (V) 0.12 HYSTCTR Setting 0.1 00 01 0 08 0.08 10 11 0.06 0.04 0.02 0 0.1 0.4 0.7 1 1.3 1.6 Vin level (V) 1.9 2.2 2.5 2.8 3.1 Figure 18. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1) 6.6.3 12-bit DAC electrical characteristics 6.6.3.1 Symbol 12-bit DAC operating requirements Table 31. 12-bit DAC operating requirements Desciption Min. Max. Unit VDDA Supply voltage 1.71 3.
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Peripheral operating requirements and behaviors 6.6.3.2 Symbol 12-bit DAC operating behaviors Table 32. 12-bit DAC operating behaviors Description IDDA_DACL Supply current — low-power mode Min. Typ. Max. Unit — — 150 μA — — 700 μA Notes P IDDA_DACH Supply current — high-speed mode P tDACLP Full-scale settling time (0x080 to 0xF7F) — low-power mode — 100 200 μs 1 tDACHP Full-scale settling time (0x080 to 0xF7F) — high-power mode — 15 30 μs 1 — 0.
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Peripheral operating requirements and behaviors Figure 19. Typical INL error vs. digital code K10 Sub-Family Data Sheet, Rev. 3, 11/2012. Freescale Semiconductor, Inc.
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Peripheral operating requirements and behaviors Figure 20. Offset at half scale vs. temperature 6.6.4 Voltage reference electrical specifications Table 33. VREF full-range operating requirements Symbol Description Min. Max. Unit VDDA Supply voltage 1.71 3.6 V TA Temperature CL Output load capacitance Operating temperature range of the device °C 100 nF Notes 1, 2 1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external reference.
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Peripheral operating requirements and behaviors Table 34. VREF full-range operating behaviors Symbol Description Min. Typ. Max. Unit Notes Vout Voltage reference output with factory trim at nominal VDDA and temperature=25C 1.1915 1.195 1.1977 V Vout Voltage reference output — factory trim 1.1584 — 1.2376 V Vout Voltage reference output — user trim 1.193 — 1.197 V Vstep Voltage reference trim step — 0.
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Peripheral operating requirements and behaviors 6.8.1 CAN switching specifications See General switching specifications. 6.8.2 DSPI switching specifications (limited voltage range) The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The tables below provide DSPI timing characteristics for classic SPI timing modes.
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Peripheral operating requirements and behaviors Table 38. Slave mode DSPI timing (limited voltage range) Num Description Operating voltage Min. Max. Unit 2.7 3.6 V 12.
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Peripheral operating requirements and behaviors Table 39. Master mode DSPI timing (full voltage range) (continued) Num Description Min. Max. Unit Notes DS2 DSPI_SCK output high/low time (tSCK/2) - 4 (tSCK/2) + 4 ns DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) − 4 — ns 2 DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) − 4 — ns 3 DS5 DSPI_SCK to DSPI_SOUT valid — 10 ns DS6 DSPI_SCK to DSPI_SOUT invalid -4.5 — ns DS7 DSPI_SIN to DSPI_SCK input setup 20.
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Peripheral operating requirements and behaviors DSPI_SS DS10 DS9 DSPI_SCK DS15 (CPOL=0) DSPI_SOUT DS12 First data DS13 DSPI_SIN DS16 DS11 Data Last data DS14 First data Data Last data Figure 24. DSPI classic SPI timing — slave mode 6.8.4 I2C switching specifications See General switching specifications. 6.8.5 UART switching specifications See General switching specifications. 6.8.
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Peripheral operating requirements and behaviors Table 41. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (full voltage range) Num. Characteristic Min. Max. Unit Operating voltage 1.71 3.
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Peripheral operating requirements and behaviors Table 42. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (full voltage range) (continued) Num. Characteristic Min. Max. Unit S13 I2S_TX_FS/I2S_RX_FS input setup before I2S_TX_BCLK/I2S_RX_BCLK 5.8 — ns S14 I2S_TX_FS/I2S_RX_FS input hold after I2S_TX_BCLK/I2S_RX_BCLK 2 — ns S16 I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid 0 — ns S17 I2S_RXD setup before I2S_RX_BCLK 5.
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Peripheral operating requirements and behaviors Table 43. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range) (continued) Num. Characteristic Min. Max.
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Peripheral operating requirements and behaviors Table 44. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range) (continued) Num. Characteristic Min. S17 I2S_RXD setup before I2S_RX_BCLK S18 I2S_RXD hold after I2S_RX_BCLK S19 I2S_TX_FS input assertion to I2S_TXD output valid1 Max. Unit 30 — ns 6.5 — ns — 72 ns 1.
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Dimensions Table 45. TSI electrical specifications (continued) Symbol IELE Description Electrode oscillator current source base current • 2 μA setting (EXTCHRG = 0) • 32 μA setting (EXTCHRG = 15) Min. Typ. Max. — 2 3 — 36 50 Unit Notes μA 2, 7 Pres5 Electrode capacitance measurement precision — 8.3333 38400 fF/count 8 Pres20 Electrode capacitance measurement precision — 8.3333 38400 fF/count 9 Pres100 Electrode capacitance measurement precision — 8.
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Pinout If you want the drawing for this package Then use this document number 100-pin LQFP 98ASS23308W 121-pin MAPBGA 98ASA00344D 8 Pinout 8.1 K10 Signal Multiplexing and Pin Assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin.
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Pinout 121 100 MAP LQFP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort J2 17 ADC1_DM1 ADC1_DM1 ADC1_DM1 K1 18 PGA0_DP/ ADC0_DP0/ ADC1_DP3 PGA0_DP/ ADC0_DP0/ ADC1_DP3 PGA0_DP/ ADC0_DP0/ ADC1_DP3 K2 19 PGA0_DM/ ADC0_DM0/ ADC1_DM3 PGA0_DM/ ADC0_DM0/ ADC1_DM3 PGA0_DM/ ADC0_DM0/ ADC1_DM3 L1 20 PGA1_DP/ ADC1_DP0/ ADC0_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3 PGA1_DP/ ADC1_DP0/ ADC0_DP3 L2 21 PGA1_DM/ ADC1_DM0/ ADC0_DM3 PGA1_DM/ ADC1_DM0/ ADC0_DM3 PGA1_DM/ ADC1_DM0/
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Pinout 121 100 MAP LQFP BGA Pin Name Default K7 39 PTA5 DISABLED ALT0 ALT1 ALT2 PTA5 ALT3 ALT4 FTM0_CH2 ALT5 CMP2_OUT ALT6 ALT7 I2S0_TX_ BCLK JTAG_TRST_ b E5 40 VDD VDD VDD G3 41 VSS VSS VSS K8 42 PTA12 CMP2_IN0 CMP2_IN0 PTA12 CAN0_TX FTM1_CH0 I2S0_TXD0 FTM1_QD_ PHA L8 43 PTA13/ LLWU_P4 CMP2_IN1 CMP2_IN1 PTA13/ LLWU_P4 CAN0_RX FTM1_CH1 I2S0_TX_FS FTM1_QD_ PHB K9 44 PTA14 DISABLED PTA14 SPI0_PCS0 UART0_TX I2S0_RX_ BCLK I2S0_TXD1 L9 45 PTA15 DISABL
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Pinout 121 100 MAP LQFP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 E9 63 PTB17 TSI0_CH10 TSI0_CH10 PTB17 SPI1_SIN UART0_TX D9 64 PTB18 TSI0_CH11 TSI0_CH11 PTB18 CAN0_TX FTM2_CH0 C9 65 PTB19 TSI0_CH12 TSI0_CH12 PTB19 CAN0_RX FTM2_CH1 F10 66 PTB20 DISABLED F9 67 PTB21 F8 68 E8 ALT4 ALT5 ALT6 FB_AD16 EWM_OUT_b I2S0_TX_ BCLK FB_AD15 FTM2_QD_ PHA I2S0_TX_FS FB_OE_b FTM2_QD_ PHB PTB20 FB_AD31 CMP0_OUT DISABLED PTB21 FB_AD30 CMP1_OUT PTB22 DISABLED PTB22
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Pinout 121 100 MAP LQFP BGA Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 C4 91 PTC17 DISABLED PTC17 UART3_TX FB_CS4_b/ FB_TSIZ0/ FB_BE31_24_ b B4 92 PTC18 DISABLED PTC18 UART3_RTS_ b FB_TBST_b/ FB_CS2_b/ FB_BE15_8_b A4 — PTC19 DISABLED PTC19 UART3_CTS_ b FB_CS3_b/ FB_BE7_0_b D4 93 PTD0/ LLWU_P12 DISABLED PTD0/ LLWU_P12 SPI0_PCS0 UART2_RTS_ b FB_ALE/ FB_CS1_b/ FB_TS_b D3 94 PTD1 ADC0_SE5b PTD1 SPI0_SCK UART2_CTS_ b FB_CS0_b C3 95 PTD2/ LLWU_P13 DISABLE
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Pinout 8.2 K10 Pinouts The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. K10 Sub-Family Data Sheet, Rev. 3, 11/2012. 68 Freescale Semiconductor, Inc.
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PTD0/LLWU_P12 PTC18 PTC17 PTC16 VDD VSS PTC15 PTC14 PTC13 PTC12 PTC11/LLWU_P11 PTC10 PTC9 PTC8 PTC7 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 PTC4/LLWU_P8 PTD1 94 76 PTD2/LLWU_P13 95 PTC6/LLWU_P10 PTD3 96 PTC5/LLWU_P9 PTD4/LLWU_P14 97 78 PTD5 77 PTD6/LLWU_P15 98 PTD7 100 99 Pinout PTE0 1 75 VDD PTE1/LLWU_P0 2 74 VSS PTE2/LLWU_P1 3 73 PTC3/LLWU_P7 PTE3 4 72 PTC2 PTE4/LLWU_P2 5 71 PTC1/LLWU_P6 PTE5 6 70 PTC0 PTE6 7 69 PTB23 VDD 8 6
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Revision History 1 2 3 4 5 6 7 8 9 10 11 A PTD7 PTD5 PTD4/ LLWU_P14 PTC19 PTC14 PTC13 PTC8 PTC4/ LLWU_P8 NC NC NC A B NC PTD6/ LLWU_P15 PTD3 PTC18 PTC15 PTC12 PTC7 PTC3/ LLWU_P7 PTC0 PTB16 NC B C NC NC PTD2/ LLWU_P13 PTC17 PTC11/ LLWU_P11 PTC10 PTC6/ LLWU_P10 PTC2 PTB19 PTB11 NC C D NC NC PTD1 PTD0/ LLWU_P12 PTC16 PTC9 PTC5/ LLWU_P9 PTC1/ LLWU_P6 PTB18 PTB10 PTB8 D E NC PTE2/ LLWU_P1 PTE1/ LLWU_P0 PTE0 VDD VDD VDD PTB23 PTB17 PTB9 PT
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Revision History Table 46. Revision History (continued) Rev. No. Date Substantial Changes 2 4/2012 • • • • • • 3 11/2012 • Updated orderable part numbers. • Updated the maximum input voltage (VADIN) specification in the "16-bit ADC operating conditions" section. Replaced TBDs throughout. Updated "Power consumption operating behaviors" table. Updated "ADC electrical specifications" section. Updated "VREF full-range operating behaviors" table. Updated "I2S/SAI Switching Specifications" section.
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