Information

5.3 Switching specifications
5.3.1 Device clock specifications
Table 8. Device clock specifications
Symbol Description Min. Max. Unit Notes
Normal run mode
f
SYS
System and core clock — 72 MHz
f
BUS
Bus clock — 50 MHz
FB_CLK FlexBus clock — 50 MHz
f
FLASH
Flash clock — 25 MHz
f
LPTMR
LPTMR clock — 25 MHz
VLPR mode
1
f
SYS
System and core clock — 4 MHz
f
BUS
Bus clock — 4 MHz
FB_CLK FlexBus clock — 4 MHz
f
FLASH
Flash clock — 0.5 MHz
f
ERCLK
External reference clock — 16 MHz
f
LPTMR_pin
LPTMR clock — 25 MHz
f
LPTMR_ERCLK
LPTMR external reference clock — 16 MHz
f
FlexCAN_ERCLK
FlexCAN external reference clock — 8 MHz
f
I2S_MCLK
I2S master clock — 12.5 MHz
f
I2S_BCLK
I2S bit clock — 4 MHz
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
other module.
5.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, CMT, and I
2
C signals.
Table 9. General switching specifications
Symbol Description Min. Max. Unit Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5 — Bus clock
cycles
1, 2
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
100 — ns 3
Table continues on the next page...
General
K10 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc. 19