Information

First data Last data

First data Data Last data

Data

DS15

DS10 DS9

DS16

DS11

DS12

DS14

DS13

DSPI_SS

DSPI_SCK

(CPOL=0)

DSPI_SOUT

DSPI_SIN

Figure 24. DSPI classic SPI timing — slave mode

6.8.4 I

C switching specifications

See General switching specifications.

6.8.5 UART switching specifications

See General switching specifications.

6.8.6 I2S/SAI Switching Specifications

This section provides the AC timing for the I2S/SAI module in master mode (clocks are

driven) and slave mode (clocks are input). All timing is given for noninverted serial clock

polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP]

is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been

inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the

frame sync (FS) signal shown in the following figures.

6.8.6.1 Normal Run, Wait and Stop mode performance over the full

operating voltage range

This section provides the operating performance over the full operating voltage for the

device in Normal Run, Wait and Stop modes.

Peripheral operating requirements and behaviors

K10 Sub-Family Data Sheet, Rev. 3, 11/2012.

Freescale Semiconductor, Inc. 57