Information

Table 44. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
(continued)
Num. Characteristic Min. Max. Unit
S17 I2S_RXD setup before I2S_RX_BCLK 30 — ns
S18 I2S_RXD hold after I2S_RX_BCLK 6.5 — ns
S19 I2S_TX_FS input assertion to I2S_TXD output valid
1
— 72 ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S15
S13
S15
S17 S18
S15
S16
S16
S14
S16
S11
S12
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
I2S_TX_FS/
I2S_RX_FS (output)
I2S_TXD
I2S_RXD
I2S_TX_FS/
I2S_RX_FS (input)
S19
Figure 28. I2S/SAI timing — slave modes
6.9 Human-machine interfaces (HMI)
6.9.1 TSI electrical specifications
Table 45. TSI electrical specifications
Symbol Description Min. Typ. Max. Unit Notes
V
DDTSI
Operating voltage 1.71 — 3.6 V
C
ELE
Target electrode capacitance range 1 20 500 pF 1
f
REFmax
Reference oscillator frequency — 8 15 MHz 2, 3
f
ELEmax
Electrode oscillator frequency — 1 1.8 MHz 2, 4
C
REF
Internal reference capacitor — 1 — pF
V
DELTA
Oscillator delta voltage — 500 — mV 2, 5
I
REF
Reference oscillator current source base current
• 2 μA setting (REFCHRG = 0)
• 32 μA setting (REFCHRG = 15)
—
—
2
36
3
50
μA 2, 6
Table continues on the next page...
Peripheral operating requirements and behaviors
K10 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc. 61