Information

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100-pin LQFP 98ASS23308W
121-pin MAPBGA 98ASA00344D
8 Pinout
8.1 K10 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
121
MAP
BGA
100
LQFP
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
E4 1 PTE0 ADC1_SE4a ADC1_SE4a PTE0 SPI1_PCS1 UART1_TX I2C1_SDA RTC_CLKOUT
E3 2 PTE1/
LLWU_P0
ADC1_SE5a ADC1_SE5a PTE1/
LLWU_P0
SPI1_SOUT UART1_RX I2C1_SCL SPI1_SIN
E2 3 PTE2/
LLWU_P1
ADC1_SE6a ADC1_SE6a PTE2/
LLWU_P1
SPI1_SCK UART1_CTS_
b
F4 4 PTE3 ADC1_SE7a ADC1_SE7a PTE3 SPI1_SIN UART1_RTS_
b
SPI1_SOUT
E7 — VDD VDD VDD
F7 — VSS VSS VSS
H7 5 PTE4/
LLWU_P2
DISABLED PTE4/
LLWU_P2
SPI1_PCS0 UART3_TX
G4 6 PTE5 DISABLED PTE5 SPI1_PCS2 UART3_RX
F3 7 PTE6 DISABLED PTE6 SPI1_PCS3 UART3_CTS_
b
I2S0_MCLK
E6 8 VDD VDD VDD
G7 9 VSS VSS VSS
F1 10 PTE16 ADC0_SE4a ADC0_SE4a PTE16 SPI0_PCS0 UART2_TX FTM_CLKIN0 FTM0_FLT3
F2 11 PTE17 ADC0_SE5a ADC0_SE5a PTE17 SPI0_SCK UART2_RX FTM_CLKIN1 LPTMR0_
ALT3
G1 12 PTE18 ADC0_SE6a ADC0_SE6a PTE18 SPI0_SOUT UART2_CTS_
b
I2C0_SDA
G2 13 PTE19 ADC0_SE7a ADC0_SE7a PTE19 SPI0_SIN UART2_RTS_
b
I2C0_SCL
L6 — VSS VSS VSS
H1 14 ADC0_DP1 ADC0_DP1 ADC0_DP1
H2 15 ADC0_DM1 ADC0_DM1 ADC0_DM1
J1 16 ADC1_DP1 ADC1_DP1 ADC1_DP1
Pinout
K10 Sub-Family Data Sheet, Rev. 3, 11/2012.
Freescale Semiconductor, Inc. 63