Information

1
A PTD7
B NC
C NC
D NC
E NC
F PTE16
G PTE18
H ADC0_DP1
J ADC1_DP1
K
PGA0_DP/
1
L
PGA1_DP/
2
PTD5
PTD6/
NC
NC
PTE2/
PTE17
PTE19
ADC0_DM1
ADC1_DM1
PGA0_DM/
2
PGA1_DM/
3
PTD4/
PTD3
PTD2/
PTD1
PTE1/
PTE6
VSS
NC
NC
NC
3
VREF_OUT/
4
PTC19
PTC18
PTC17
PTD0/
PTE0
PTE3
PTE5
NC
NC
NC
4
XTAL32
5
PTC14
PTC15
PTC11/
PTC16
VDD
VDDA
VREFH
PTE24
PTE25
DAC0_OUT/
5
EXTAL32
6
PTC13
PTC12
PTC10
PTC9
VDD
VSSA
VREFL
PTE26
PTA0
VBAT
6
VSS
7
PTC8
PTC7
PTC6/
PTC5/
VDD
VSS
VSS
PTE4/
PTA2
PTA5
7
RTC_
8
PTC4/
PTC3/
PTC2
PTC1/
PTB23
PTB22
PTB3
PTA1
PTA4/
PTA12
8
PTA13/
9
NC
PTC0
PTB19
PTB18
PTB17
PTB21
PTB2
PTA3
NC
PTA14
9
PTA15
10
NC
PTB16
PTB11
PTB10
PTB9
PTB20
PTB1
PTA17
PTA16
VSS
10
VDD
11
ANC
BNC
CNC
DPTB8
EPTB7
FPTB6
G
PTB0/
HNC
JRESET_b
KPTA19
11
LPTA18
LLWU_P14 LLWU_P8
LLWU_P15 LLWU_P7
LLWU_P13 LLWU_P11 LLWU_P10
LLWU_P12 LLWU_P9 LLWU_P6
LLWU_P1 LLWU_P0
LLWU_P5
LLWU_P3
ADC0_DM0/
ADC1_DM3
ADC0_DP0/
ADC1_DP3
CMP1_IN3/
ADC0_SE23
WAKEUP_B LLWU_P4
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
ADC1_DM0/
ADC0_DM3
ADC1_DP0/
ADC0_DP3
LLWU_P2
Figure 30. K10 121 MAPBGA Pinout Diagram
9 Revision History
The following table provides a revision history for this document.
Table 46. Revision History
Rev. No. Date Substantial Changes
1 3/2012 Initial public release
Table continues on the next page...
Revision History
K10 Sub-Family Data Sheet, Rev. 3, 11/2012.
70 Freescale Semiconductor, Inc.