Datasheet

6.3.1 MCG specifications
Table 15. MCG specifications
Symbol Description Min. Typ. Max. Unit Notes
f
ints_ft
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
— 32.768 — kHz
f
ints_t
Internal reference frequency (slow clock) — user
trimmed — over fixed voltage and temperature
range of 0–70°C
31.25 — 38.2 kHz
Δ
fdco_res_t
Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
— ± 0.3 ± 0.6 %f
dco
1
Δf
dco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
— ± 1.5 ± 4.5 %f
dco
1
f
intf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
— 4 — MHz
f
intf_t
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
3 — 5 MHz
f
loc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
f
ints_t
— — kHz
f
loc_high
Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
f
ints_t
— — kHz
FLL
f
fll_ref
FLL reference frequency range 31.25 — 39.0625 kHz
f
dco
DCO output
frequency range
Low range (DRS=00)
640 × f
fll_ref
20 20.97 25 MHz 2, 3
Mid range (DRS=01)
1280 × f
fll_ref
40 41.94 50 MHz
Mid-high range (DRS=10)
1920 × f
fll_ref
60 62.91 75 MHz
High range (DRS=11)
2560 × f
fll_ref
80 83.89 100 MHz
f
dco_t_DMX32
DCO output
frequency
Low range (DRS=00)
732 × f
fll_ref
— 23.99 — MHz 4, 5
Mid range (DRS=01)
1464 × f
fll_ref
— 47.97 — MHz
Mid-high range (DRS=10)
2197 × f
fll_ref
— 71.99 — MHz
High range (DRS=11)
2929 × f
fll_ref
— 95.98 — MHz
J
cyc_fll
FLL period jitter
• f
VCO
= 48 MHz
• f
VCO
= 98 MHz
—
—
180
150
—
—
ps
t
fll_acquire
FLL target frequency acquisition time — — 1 ms 6
Table continues on the next page...
Peripheral operating requirements and behaviors
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
28 Freescale Semiconductor, Inc.