Datasheet

121
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
E3 PTE1/
LLWU_P0
ADC1_SE5a ADC1_SE5a PTE1/
LLWU_P0
SPI1_SOUT UART1_RX SDHC0_D0 I2C1_SCL
E2 PTE2/
LLWU_P1
ADC1_SE6a ADC1_SE6a PTE2/
LLWU_P1
SPI1_SCK UART1_CTS_b SDHC0_DCLK
F4 PTE3 ADC1_SE7a ADC1_SE7a PTE3 SPI1_SIN UART1_RTS_b SDHC0_CMD
E7 VDD VDD VDD
F7 VSS VSS VSS
H7 PTE4/
LLWU_P2
DISABLED PTE4/
LLWU_P2
SPI1_PCS0 UART3_TX SDHC0_D3
G4 PTE5 DISABLED PTE5 SPI1_PCS2 UART3_RX SDHC0_D2
F3 PTE6 DISABLED PTE6 SPI1_PCS3 UART3_CTS_b I2S0_MCLK I2S0_CLKIN
E6 VDD VDD VDD
G7 VSS VSS VSS
L6 VSS VSS VSS
F1 USB0_DP USB0_DP USB0_DP
F2 USB0_DM USB0_DM USB0_DM
G1 VOUT33 VOUT33 VOUT33
G2 VREGIN VREGIN VREGIN
H1 ADC0_DP1 ADC0_DP1 ADC0_DP1
H2 ADC0_DM1 ADC0_DM1 ADC0_DM1
J1 ADC1_DP1 ADC1_DP1 ADC1_DP1
J2 ADC1_DM1 ADC1_DM1 ADC1_DM1
K1 PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
K2 PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
L1 PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
L2 PGA1_DM/
ADC1_DM0/
ADC0_DM3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
F5 VDDA VDDA VDDA
G5 VREFH VREFH VREFH
G6 VREFL VREFL VREFL
F6 VSSA VSSA VSSA
J3 ADC1_SE16/
CMP2_IN2/
ADC0_SE22
ADC1_SE16/
CMP2_IN2/
ADC0_SE22
ADC1_SE16/
CMP2_IN2/
ADC0_SE22
H3 ADC0_SE16/
CMP1_IN2/
ADC0_SE21
ADC0_SE16/
CMP1_IN2/
ADC0_SE21
ADC0_SE16/
CMP1_IN2/
ADC0_SE21
Pinout
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
Freescale Semiconductor, Inc. 67