Datasheet

121
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
L3 VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
K5 DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
K4 DAC1_OUT/
CMP2_IN3/
ADC1_SE23
DAC1_OUT/
CMP2_IN3/
ADC1_SE23
DAC1_OUT/
CMP2_IN3/
ADC1_SE23
L4 XTAL32 XTAL32 XTAL32
L5 EXTAL32 EXTAL32 EXTAL32
K6 VBAT VBAT VBAT
H5 PTE24 ADC0_SE17 ADC0_SE17 PTE24 CAN1_TX UART4_TX EWM_OUT_b
J5 PTE25 ADC0_SE18 ADC0_SE18 PTE25 CAN1_RX UART4_RX EWM_IN
H6 PTE26 DISABLED PTE26 UART4_CTS_b RTC_CLKOUT USB_CLKIN
J6 PTA0 JTAG_TCLK/
SWD_CLK/
EZP_CLK
TSI0_CH1 PTA0 UART0_CTS_b FTM0_CH5 JTAG_TCLK/
SWD_CLK
EZP_CLK
H8 PTA1 JTAG_TDI/
EZP_DI
TSI0_CH2 PTA1 UART0_RX FTM0_CH6 JTAG_TDI EZP_DI
J7 PTA2 JTAG_TDO/
TRACE_SWO/
EZP_DO
TSI0_CH3 PTA2 UART0_TX FTM0_CH7 JTAG_TDO/
TRACE_SWO
EZP_DO
H9 PTA3 JTAG_TMS/
SWD_DIO
TSI0_CH4 PTA3 UART0_RTS_b FTM0_CH0 JTAG_TMS/
SWD_DIO
J8 PTA4/
LLWU_P3
NMI_b/
EZP_CS_b
TSI0_CH5 PTA4/
LLWU_P3
FTM0_CH1 NMI_b EZP_CS_b
K7 PTA5 DISABLED PTA5 FTM0_CH2 CMP2_OUT I2S0_RX_BCLK JTAG_TRST
E5 VDD VDD VDD
G3 VSS VSS VSS
J9 PTA10 DISABLED PTA10 FTM2_CH0 FTM2_QD_
PHA
TRACE_D0
J4 PTA11 DISABLED PTA11 FTM2_CH1 FTM2_QD_
PHB
K8 PTA12 CMP2_IN0 CMP2_IN0 PTA12 CAN0_TX FTM1_CH0 I2S0_TXD FTM1_QD_
PHA
L8 PTA13/
LLWU_P4
CMP2_IN1 CMP2_IN1 PTA13/
LLWU_P4
CAN0_RX FTM1_CH1 I2S0_TX_FS FTM1_QD_
PHB
K9 PTA14 DISABLED PTA14 SPI0_PCS0 UART0_TX I2S0_TX_BCLK
L9 PTA15 DISABLED PTA15 SPI0_SCK UART0_RX I2S0_RXD
J10 PTA16 DISABLED PTA16 SPI0_SOUT UART0_CTS_b I2S0_RX_FS
H10 PTA17 ADC1_SE17 ADC1_SE17 PTA17 SPI0_SIN UART0_RTS_b I2S0_MCLK I2S0_CLKIN
L10 VDD VDD VDD
K10 VSS VSS VSS
L11 PTA18 EXTAL EXTAL PTA18 FTM0_FLT2 FTM_CLKIN0
Pinout
K20 Sub-Family Data Sheet Data Sheet, Rev. 7, 02/2013.
68 Freescale Semiconductor, Inc.