Information

Master
mode?
Tx/Rx?
Arbitration
lost?
IAAS=1?
Tx/Rx?
ACK from
receiver?
SRW=1?
IAAS=1?
Clear ARBL
2nd to
last byte to be
read?
Last byte
to be read?
RXAK=0?
Last byte
transmitted?
End of
address cycle
(master Rx)?
Write next
byte to Data reg
Generate stop
signal (MST=0)
Set TXAK to
proper value
Clear IICIF
Delay (note 2)
Delay (note 2)
Read data from
Data reg
and soft CRC
Transmit
next byte
RTI
Switch to
Rx mode
Switch to
Rx mode
Dummy read
from Data reg
Generate stop
signal (MST=0)
Read data from
Data reg
and store
Read data from
Data reg
and store
Dummy read
from Data reg
N
Y
N
N
N
N
N
N
Y
Y
Y
Y
Y
(read)
N (write)
N
Y
RxTx
Rx
Tx
Y
N
Address transfer
see note 1
N
Y
Y
Y
SLTF or
SHTF2=1?
N
Y
Clear IICIF
FACK=1?
N
Y
See typical I2C
interrupt routine
flow chart
Set TXAK to
proper value
Clear IICIF
Delay (note 2)
Set Tx mode
Write data
to Data reg
Clear IICIF
Notes:
1. If general call or SIICAEN is enabled, check to determine if the received address is a general call address (0x00) or an SMBus
device default address. In either case, they must be handled by user software.
2. In receive mode, one bit time delay may be needed before the first and second data reading.
Clear IICIF
Delay (note 2)
Read data from
Data reg
and soft CRC
Set TXAK to
proper value
Clear IICIF
Delay (note 2)
Delay (note 2)
Read data from
Data reg
and soft CRC
Set TXACK=1
Clear FACK=0
Delay (note 2)
Read data and
Soft CRC
Set TXAK to
proper value
Delay (note 2)
Figure 44-31. Typical I2C SMBus interrupt routine
Chapter 44 Inter-Integrated Circuit (I2C)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 1037