Information

3.8.1.5 Pulse-Out Enable Register Implementation
The following table shows the comparison of pulse-out enable register at the module and
chip level.
Table 3-44. PDB pulse-out enable register
Register Module implementation Chip implementation
POnEN 7:0 - POEN
31:8 - Reserved
0 - POEN[0] for CMP0
1 - POEN[1] for CMP1
31:2 - Reserved
3.8.2 FlexTimer Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Signal multiplexing
Module signals
Register
access
FlexTimer
Peripheral bus
controller 0
Other peripherals
Transfers
Figure 3-34. FlexTimer configuration
Table 3-45. Reference links to related information
Topic Related module Reference
Full description FlexTimer FlexTimer
System memory map System memory map
Clocking Clock distribution
Power management Power management
Signal multiplexing Port control Signal multiplexing
3.8.2.1 Instantiation Information
This device contains two FlexTimer modules.
The following table shows how these modules are configured.
Timers
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
104 Freescale Semiconductor, Inc.