Information

UART memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4006_A024 UART CEA709.1-B Beta1 Timer (UART0_B1T) 8 R/W 00h
45.3.35/
1086
4006_A025
UART CEA709.1-B Secondary Delay Timer High
(UART0_SDTH)
8 R/W 00h
45.3.36/
1087
4006_A026
UART CEA709.1-B Secondary Delay Timer Low
(UART0_SDTL)
8 R/W 00h
45.3.37/
1087
4006_A027 UART CEA709.1-B Preamble (UART0_PRE) 8 R/W 00h
45.3.38/
1088
4006_A028 UART CEA709.1-B Transmit Packet Length (UART0_TPL) 8 R/W 00h
45.3.39/
1088
4006_A029 UART CEA709.1-B Interrupt Enable Register (UART0_IE) 8 R/W 00h
45.3.40/
1089
4006_A02A UART CEA709.1-B WBASE (UART0_WB) 8 R/W 00h
45.3.41/
1090
4006_A02B UART CEA709.1-B Status Register (UART0_S3) 8 R/W 00h
45.3.42/
1090
4006_A02C UART CEA709.1-B Status Register (UART0_S4) 8 R/W 00h
45.3.43/
1092
4006_A02D UART CEA709.1-B Received Packet Length (UART0_RPL) 8 R 00h
45.3.44/
1093
4006_A02E
UART CEA709.1-B Received Preamble Length
(UART0_RPREL)
8 R 00h
45.3.45/
1093
4006_A02F UART CEA709.1-B Collision Pulse Width (UART0_CPW) 8 R/W 00h
45.3.46/
1094
4006_A030
UART CEA709.1-B Receive Indeterminate Time
(UART0_RIDT)
8 R/W 00h
45.3.47/
1094
4006_A031
UART CEA709.1-B Transmit Indeterminate Time
(UART0_TIDT)
8 R/W 00h
45.3.48/
1095
4006_B000 UART Baud Rate Registers: High (UART1_BDH) 8 R/W 00h
45.3.1/
1051
4006_B001 UART Baud Rate Registers: Low (UART1_BDL) 8 R/W 04h
45.3.2/
1052
4006_B002 UART Control Register 1 (UART1_C1) 8 R/W 00h
45.3.3/
1053
4006_B003 UART Control Register 2 (UART1_C2) 8 R/W 00h
45.3.4/
1055
4006_B004 UART Status Register 1 (UART1_S1) 8 R C0h
45.3.5/
1056
4006_B005 UART Status Register 2 (UART1_S2) 8 R/W 00h
45.3.6/
1059
Table continues on the next page...
Memory map and registers
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
1046 Freescale Semiconductor, Inc.