Information

UART memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4006_C013 UART FIFO Transmit Watermark (UART2_TWFIFO) 8 R/W 00h
45.3.19/
1074
4006_C014 UART FIFO Transmit Count (UART2_TCFIFO) 8 R 00h
45.3.20/
1075
4006_C015 UART FIFO Receive Watermark (UART2_RWFIFO) 8 R/W 01h
45.3.21/
1075
4006_C016 UART FIFO Receive Count (UART2_RCFIFO) 8 R 00h
45.3.22/
1076
4006_C018 UART 7816 Control Register (UART2_C7816) 8 R/W 00h
45.3.23/
1076
4006_C019 UART 7816 Interrupt Enable Register (UART2_IE7816) 8 R/W 00h
45.3.24/
1078
4006_C01A UART 7816 Interrupt Status Register (UART2_IS7816) 8 R/W 00h
45.3.25/
1079
4006_C01B UART 7816 Wait Parameter Register (UART2_WP7816T0) 8 R/W 0Ah
45.3.26/
1081
4006_C01B UART 7816 Wait Parameter Register (UART2_WP7816T1) 8 R/W 0Ah
45.3.27/
1081
4006_C01C UART 7816 Wait N Register (UART2_WN7816) 8 R/W 00h
45.3.28/
1082
4006_C01D UART 7816 Wait FD Register (UART2_WF7816) 8 R/W 01h
45.3.29/
1082
4006_C01E UART 7816 Error Threshold Register (UART2_ET7816) 8 R/W 00h
45.3.30/
1083
4006_C01F UART 7816 Transmit Length Register (UART2_TL7816) 8 R/W 00h
45.3.31/
1084
4006_C021 UART CEA709.1-B Control Register 6 (UART2_C6) 8 R/W 00h
45.3.32/
1084
4006_C022
UART CEA709.1-B Packet Cycle Time Counter High
(UART2_PCTH)
8 R/W 00h
45.3.33/
1085
4006_C023
UART CEA709.1-B Packet Cycle Time Counter Low
(UART2_PCTL)
8 R/W 00h
45.3.34/
1086
4006_C024 UART CEA709.1-B Beta1 Timer (UART2_B1T) 8 R/W 00h
45.3.35/
1086
4006_C025
UART CEA709.1-B Secondary Delay Timer High
(UART2_SDTH)
8 R/W 00h
45.3.36/
1087
4006_C026
UART CEA709.1-B Secondary Delay Timer Low
(UART2_SDTL)
8 R/W 00h
45.3.37/
1087
4006_C027 UART CEA709.1-B Preamble (UART2_PRE) 8 R/W 00h
45.3.38/
1088
Table continues on the next page...
Memory map and registers
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
1050 Freescale Semiconductor, Inc.