Information

45.3.4 UART Control Register 2 (UARTx_C2)
This register can be read or written at any time.
Addresses: UART0_C2 is 4006_A000h base + 3h offset = 4006_A003h
UART1_C2 is 4006_B000h base + 3h offset = 4006_B003h
UART2_C2 is 4006_C000h base + 3h offset = 4006_C003h
Bit 7 6 5 4 3 2 1 0
Read
TIE TCIE RIE ILIE TE RE RWU SBK
Write
Reset
0 0 0 0 0 0 0 0
UARTx_C2 field descriptions
Field Description
7
TIE
Transmitter Interrupt or DMA Transfer Enable.
Enables S1[TDRE] to generate interrupt requests or DMA transfer requests, based on the state of
C5[TDMAS].
NOTE: If C2[TIE] and C5[TDMAS] are both set, then TCIE must be cleared, and D[D] must not be
written unless servicing a DMA request.
0 TDRE interrupt and DMA transfer requests disabled.
1 TDRE interrupt or DMA transfer requests enabled.
6
TCIE
Transmission Complete Interrupt Enable
Enables the transmission complete flag, S1[TC], to generate interrupt requests .
0 TC interrupt requests disabled.
1
TC interrupt requests enabled.
5
RIE
Receiver Full Interrupt or DMA Transfer Enable
Enables S1[RDRF] to generate interrupt requests or DMA transfer requests, based on the state of
C5[RDMAS].
0 RDRF interrupt and DMA transfer requests disabled.
1 RDRF interrupt or DMA transfer requests enabled.
4
ILIE
Idle Line Interrupt Enable
Enables the idle line flag, S1[IDLE], to generate interrupt requests , based on the state of C5[ILDMAS].
0 IDLE interrupt requests disabled.
1 IDLE interrupt requests enabled.
3
TE
Transmitter Enable
Enables the UART transmitter. TE can be used to queue an idle preamble by clearing and then setting
TE. When C7816[ISO_7816E] is set/enabled and C7816[TTYPE] = 1, this field is automatically cleared
after the requested block has been transmitted. This condition is detected when TL7816[TLEN] = 0 and
four additional characters are transmitted.
Table continues on the next page...
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 1055