Information

NOTE
• If the condition that results in the assertion of the flag,
interrupt, or DMA request is not resolved prior to clearing
the flag, the flag, and interrupt/DMA request, reasserts. For
example, if the DMA or interrupt service routine fails to
write sufficient data to the transmit buffer to raise it above
the watermark level, the flag reasserts and generates
another interrupt or DMA request.
• Reading an empty data register to clear one of the flags of
the S1 register causes the FIFO pointers to become
misaligned. A receive FIFO flush reinitializes the pointers.
Addresses: UART0_S1 is 4006_A000h base + 4h offset = 4006_A004h
UART1_S1 is 4006_B000h base + 4h offset = 4006_B004h
UART2_S1 is 4006_C000h base + 4h offset = 4006_C004h
Bit 7 6 5 4 3 2 1 0
Read TDRE TC RDRF IDLE OR NF FE PF
Write
Reset
1 1 0 0 0 0 0 0
UARTx_S1 field descriptions
Field Description
7
TDRE
Transmit Data Register Empty Flag
TDRE will set when the number of datawords in the transmit buffer (D and C3[T8])is equal to or less than
the number indicated by TWFIFO[TXWATER]. A character that is in the process of being transmitted is
not included in the count. To clear TDRE, read S1 when TDRE is set and then write to the UART data
register (D). For more efficient interrupt servicing, all data except the final value to be written to the buffer
must be written to D/C3[T8]. Then S1 can be read before writing the final data value, resulting in the
clearing of the TRDE flag. This is more efficient because the TDRE reasserts until the watermark has
been exceeded. So, attempting to clear the TDRE with every write will be ineffective until sufficient data
has been written.
0 The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].
1 The amount of data in the transmit buffer is less than or equal to the value indicated by
TWFIFO[TXWATER] at some point in time since the flag has been cleared.
6
TC
Transmit Complete Flag
TC is cleared when there is a transmission in progress or when a preamble or break character is loaded.
TC is set when the transmit buffer is empty and no data, preamble, or break character is being
transmitted. When TC is set, the transmit data output signal becomes idle (logic 1). TC is cleared by
reading S1 with TC set and then doing one of the following: When C7816[ISO_7816E] is set/enabled, this
field is set after any NACK signal has been received, but prior to any corresponding guard times
expiring.When C6[EN709] is set/enabled, this flag is not set on transmit packet completion.
• Writing to D to transmit new data.
• Queuing a preamble by clearing and then setting C2[TE].
• Queuing a break character by writing 1 to SBK in C2.
Table continues on the next page...
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 1057