Information
UARTx_S1 field descriptions (continued)
Field Description
in the buffer that was received with noise unless the receive buffer has a depth of one. To clear NF, read
S1 and then read D. When EN709 is set/enabled, noise flag is not set.
0 No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater
than 1 then there may be data in the receiver buffer that was received with noise.
1 At least one dataword was received with noise detected since the last time the flag was cleared.
1
FE
Framing Error Flag
FE is set when a logic 0 is accepted as the stop bit. FE does not set in the case of an overrun or while the
LIN break detect feature is enabled (S2[LBKDE] = 1). FE inhibits further data reception until it is cleared.
To clear FE, read S1 with FE set and then read D. The last data in the receive buffer represents the data
that was received with the frame error enabled. Framing errors are not supported when 7816E is set/
enabled. However, if this flag is set, data is still not received in 7816 mode.Framing errors are not
supported in 709 mode.
0 No framing error detected.
1 Framing error.
0
PF
Parity Error Flag
PF is set when PE is set, S2[LBKDE] is disabled, and the parity of the received data does not match its
parity bit. The PF is not set in the case of an overrun condition. When PF is set, it indicates only that a
dataword was received with parity error since the last time it was cleared. There is no guarantee that the
first dataword read from the receive buffer has a parity error or that there is only one dataword in the
buffer that was received with a parity error, unless the receive buffer has a depth of one. To clear PF,
read S1 and then read D. Within the receive buffer structure the received dataword is tagged if it is
received with a parity error. This information is available by reading the ED register prior to reading the D
register.When EN709 is set/enabled parity error flag is not set.
0 No parity error detected since the last time this flag was cleared. If the receive buffer has a depth
greater than 1, then there may be data in the receive buffer what was received with a parity error.
1 At least one dataword was received with a parity error since the last time this flag was cleared.
45.3.6 UART Status Register 2 (UARTx_S2)
The S2 register provides inputs to the MCU for generation of UART interrupts or DMA
requests. Also, this register can be polled by the MCU to check the status of these bits.
This register can be read or written at any time, with the exception of the MSBF and
RXINV bits, which should be changed by the user only between transmit and receive
packets.
Addresses: UART0_S2 is 4006_A000h base + 5h offset = 4006_A005h
UART1_S2 is 4006_B000h base + 5h offset = 4006_B005h
UART2_S2 is 4006_C000h base + 5h offset = 4006_C005h
Bit 7 6 5 4 3 2 1 0
Read
LBKDIF RXEDGIF MSBF RXINV RWUID BRK13 LBKDE
RAF
Write
Reset
0 0 0 0 0 0 0 0
Chapter 45 Universal Asynchronous Receiver/Transmitter (UART)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 1059