Information

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFN 48 EP (7x7) 32-Bit 50 MHz I/O number 29

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UARTx_PFIFO field descriptions (continued)

Field Description

When this field is set, the built in FIFO structure for the transmit buffer is enabled. The size of the FIFO

structure is indicated by TXFIFOSIZE. If this field is not set, the transmit buffer operates as a FIFO of

depth one dataword regardless of the value in TXFIFOSIZE. Both C2[TE] and C2[RE] must be cleared

prior to changing this field. Additionally, TXFLUSH and RXFLUSH commands must be issued immediately

after changing this field.

0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).

1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.

6–4

TXFIFOSIZE

Transmit FIFO. Buffer Depth

The maximum number of transmit datawords that can be stored in the transmit buffer. This field is read

only.

000 Transmit FIFO/Buffer depth = 1 dataword.

001 Transmit FIFO/Buffer depth = 4 datawords.

010 Transmit FIFO/Buffer depth = 8 datawords.

011 Transmit FIFO/Buffer depth = 16 datawords.

100 Transmit FIFO/Buffer depth = 32 datawords.

101 Transmit FIFO/Buffer depth = 64 datawords.

110 Transmit FIFO/Buffer depth = 128 datawords.

111 Reserved.

RXFE

Receive FIFO Enable

When this field is set, the built in FIFO structure for the receive buffer is enabled. The size of the FIFO

structure is indicated by the RXFIFOSIZE field. If this field is not set, the receive buffer operates as a

FIFO of depth one dataword regardless of the value in RXFIFOSIZE. Both C2[TE] and C2[RE] must be

cleared prior to changing this field. Additionally, TXFLUSH and RXFLUSH commands must be issued

immediately after changing this field.

0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)

1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.

2–0

RXFIFOSIZE

Receive FIFO. Buffer Depth

The maximum number of receive datawords that can be stored in the receive buffer before an overrun

occurs. This field is read only.

000 Receive FIFO/Buffer depth = 1 dataword.

001 Receive FIFO/Buffer depth = 4 datawords.

010 Receive FIFO/Buffer depth = 8 datawords.

011 Receive FIFO/Buffer depth = 16 datawords.

100 Receive FIFO/Buffer depth = 32 datawords.

101 Receive FIFO/Buffer depth = 64 datawords.

110 Receive FIFO/Buffer depth = 128 datawords.

111 Reserved.

Chapter 45 Universal Asynchronous Receiver/Transmitter (UART)

K20 Sub-Family Reference Manual, Rev. 2, Feb 2012

Freescale Semiconductor, Inc. 1071