Information

45.3.17 UART FIFO Control Register (UARTx_CFIFO)
This register provides the ability to program various control fields for FIFO operation.
This register may be read or written at any time. Note that writing to TXFLUSH and
RXFLUSH may result in data loss and requires careful action to prevent unintended/
unpredictable behavior. Therefore, it is recommended that TE and RE be cleared prior to
flushing the corresponding FIFO.
Addresses: UART0_CFIFO is 4006_A000h base + 11h offset = 4006_A011h
UART1_CFIFO is 4006_B000h base + 11h offset = 4006_B011h
UART2_CFIFO is 4006_C000h base + 11h offset = 4006_C011h
Bit 7 6 5 4 3 2 1 0
Read 0 0 0
RXOFE TXOFE RXUFE
Write TXFLUSH RXFLUSH
Reset
0 0 0 0 0 0 0 0
UARTx_CFIFO field descriptions
Field Description
7
TXFLUSH
Transmit FIFO/Buffer Flush
Writing to this field causes all data that is stored in the transmit FIFO/buffer to be flushed. This does not
affect data that is in the transmit shift register.
0 No flush operation occurs.
1 All data in the transmit FIFO/Buffer is cleared out.
6
RXFLUSH
Receive FIFO/Buffer Flush
Writing to this field causes all data that is stored in the receive FIFO/buffer to be flushed. This does not
affect data that is in the receive shift register.
0 No flush operation occurs.
1 All data in the receive FIFO/buffer is cleared out.
5–3
Reserved
This read-only field is reserved and always has the value zero.
2
RXOFE
Receive FIFO Overflow Interrupt Enable
When this field is set, the RXOF flag generates an interrupt to the host.
0 RXOF flag does not generate an interrupt to the host.
1 RXOF flag generates an interrupt to the host.
1
TXOFE
Transmit FIFO Overflow Interrupt Enable
When this field is set, the TXOF flag generates an interrupt to the host.
0 TXOF flag does not generate an interrupt to the host.
1 TXOF flag generates an interrupt to the host.
Table continues on the next page...
Memory map and registers
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
1072 Freescale Semiconductor, Inc.