Information
UARTx_SFIFO field descriptions (continued)
Field Description
0 No receive buffer overflow has occurred since the last time the flag was cleared.
1 At least one receive buffer overflow has occurred since the last time the flag was cleared.
1
TXOF
Transmitter Buffer Overflow Flag
Indicates that more data has been written to the transmit buffer than it can hold. This field will assert
regardless of the value of CFIFO[TXOFE]. However, an interrupt will be issued to the host only if
CFIFO[TXOFE] is set. This flag is cleared by writing a 1.
0 No transmit buffer overflow has occurred since the last time the flag was cleared.
1 At least one transmit buffer overflow has occurred since the last time the flag was cleared.
0
RXUF
Receiver Buffer Underflow Flag
Indicates that more data has been read from the receive buffer than was present. This field will assert
regardless of the value of CFIFO[RXUFE]. However, an interrupt will be issued to the host only if
CFIFO[RXUFE] is set. This flag is cleared by writing a 1.
0 No receive buffer underflow has occurred since the last time the flag was cleared.
1 At least one receive buffer underflow has occurred since the last time the flag was cleared.
45.3.19 UART FIFO Transmit Watermark (UARTx_TWFIFO)
This register provides the ability to set a programmable threshold for notification of
needing additional transmit data. This register may be read at any time but must be
written only when C2[TE] is not set. Changing the value of the watermark will not clear
the S1[TDRE] flag.
Addresses: UART0_TWFIFO is 4006_A000h base + 13h offset = 4006_A013h
UART1_TWFIFO is 4006_B000h base + 13h offset = 4006_B013h
UART2_TWFIFO is 4006_C000h base + 13h offset = 4006_C013h
Bit 7 6 5 4 3 2 1 0
Read
TXWATER
Write
Reset
0 0 0 0 0 0 0 0
UARTx_TWFIFO field descriptions
Field Description
7–0
TXWATER
Transmit Watermark
When the number of datawords in the transmit FIFO/buffer is equal to or less than the value in this
register field, an interrupt via S1[TDRE] or a DMA request via C5[TDMAS] is generated as determined by
C5[TDMAS] and C2[TIE]. For proper operation, the value in TXWATER must be set to be less than the
size of the transmit buffer/FIFO size as indicated by PFIFO[TXFIFOSIZE] and PFIFO[TXFE].
Memory map and registers
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
1074 Freescale Semiconductor, Inc.