Information

UARTx_RPREL field descriptions (continued)
Field Description
Indicates the number of bit sync fields received in the preamble.
45.3.46 UART CEA709.1-B Collision Pulse Width (UARTx_CPW)
Addresses: UART0_CPW is 4006_A000h base + 2Fh offset = 4006_A02Fh
UART1_CPW is 4006_B000h base + 2Fh offset = 4006_B02Fh
UART2_CPW is 4006_C000h base + 2Fh offset = 4006_C02Fh
Bit 7 6 5 4 3 2 1 0
Read
CPW
Write
Reset
0 0 0 0 0 0 0 0
UARTx_CPW field descriptions
Field Description
7–0
CPW
CEA709.1-B CPW register
Indicates the width of valid collision pulse in terms of IPG clock cycles.
45.3.47 UART CEA709.1-B Receive Indeterminate Time
(UARTx_RIDT)
Addresses: UART0_RIDT is 4006_A000h base + 30h offset = 4006_A030h
UART1_RIDT is 4006_B000h base + 30h offset = 4006_B030h
UART2_RIDT is 4006_C000h base + 30h offset = 4006_C030h
Bit 7 6 5 4 3 2 1 0
Read
RIDT
Write
Reset
0 0 0 0 0 0 0 0
UARTx_RIDT field descriptions
Field Description
7–0
RIDT
CEA709.1-B Receive IDT register
Indicates the indeterminate time period after reception during which any activity on RX line will be
discarded. Indeterminate time period value should be less than Beta1 timer value.
Memory map and registers
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
1094 Freescale Semiconductor, Inc.