Information

45.4.3.6 Hardware flow control

To support hardware flow control, the receiver can be programmed to automatically

deassert and assert RTS.

• RTS remains asserted until the transfer is complete, even if the transmitter is disabled

midway through a data transfer. See Transceiver driver enable using RTS for more

details.

• If the receiver request-to-send functionality is enabled, the receiver automatically

deasserts RTS if the number of characters in the receiver data register is equal to or

greater than receiver data buffer's watermark, RWFIFO[RXWATER].

• The receiver asserts RTS when the number of characters in the receiver data register

is less than the watermark. It is not affected if RDRF is asserted.

• Even if RTS is deasserted, the receiver continues to receive characters until the

receiver data buffer is full or is overrun.

• If the receiver request-to-send functionality is disabled, the receiver RTS remains

deasserted.

The following figure shows receiver hardware flow control functional timing. Along with

the actual character itself, RXD shows the start bit. The stop bit can also indicated, with a

dashed line, if necessary. The watermark is set to 2.

RXD

data

buffer

read

S1[RDRF]

RTS_B

C1 in reception

Status

read

C1 C2

Figure 45-201. Receiver hardware flow control timing diagram

Chapter 45 Universal Asynchronous Receiver/Transmitter (UART)

K20 Sub-Family Reference Manual, Rev. 2, Feb 2012

Freescale Semiconductor, Inc. 1115