Information

45.4.3.9.3 Match address operation
Match address operation is enabled when C4[MAEN1] or C4[MAEN2] is set. In this
function, a frame received by the RX pin with a logic 1 in the bit position immediately
preceding the stop bit is considered an address and is compared with the associated MA1
or MA2 register. The frame is transferred to the receive buffer, and S1[RDRF] is set, only
if the comparison matches. All subsequent frames received with a logic 0 in the bit
position immediately preceding the stop bit are considered to be data associated with the
address and are transferred to the receive data buffer. If no marked address match occurs,
then no transfer is made to the receive data buffer, and all following frames with logic 0
in the bit position immediately preceding the stop bit are also discarded. If both
C4[MAEN1] and C4[MAEN2] are negated, the receiver operates normally and all data
received is transferred to the receive data buffer.
Match address operation functions in the same way for both MA1 and MA2 registers.
• If only one of C4[MAEN1] and C4[MAEN2] is asserted, a marked address is
compared only with the associated match register and data is transferred to the
receive data buffer only on a match.
• If C4[MAEN1] and C4[MAEN2] are asserted, a marked address is compared with
both match registers and data is transferred only on a match with either register.
Address match operation is not supported when C7816[ISO_7816E] is set/enabled.
45.4.4 Baud rate generation
A 13-bit modulus counter and a 5-bit fractional fine-adjust counter in the baud rate
generator derive the baud rate for both the receiver and the transmitter. The value from 1
to 8191 written to SBR[12:0] determines the module clock divisor. The SBR bits are in
the UART baud rate registers, BDH and BDL. The baud rate clock is synchronized with
the module clock and drives the receiver. The fractional fine-adjust counter adds
fractional delays to the baud rate clock to allow fine trimming of the baud rate to match
the system baud rate. The transmitter is driven by the baud rate clock divided by 16. The
receiver has an acquisition rate of 16 samples per bit time.
Baud rate generation is subject to two sources of error:
• Integer division of the module clock may not give the exact target frequency. This
error can be reduced with the fine-adjust counter.
• Synchronization with the module clock can cause phase shift.
The Table 45-204 lists the available baud divisor fine adjust values.
Functional description
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
1120 Freescale Semiconductor, Inc.