Information

46.3 Memory map and register definition
A read or write access to an address after the last register will result in a bus error.
I2S memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4002_F000 SAI Transmit Control Register (I2S0_TCSR) 32 R/W 0000_0000h
46.3.1/
1147
4002_F004 SAI Transmit Configuration 1 Register (I2S0_TCR1) 32 R/W 0000_0000h
46.3.2/
1150
4002_F008 SAI Transmit Configuration 2 Register (I2S0_TCR2) 32 R/W 0000_0000h
46.3.3/
1150
4002_F00C SAI Transmit Configuration 3 Register (I2S0_TCR3) 32 R/W 0000_0000h
46.3.4/
1152
4002_F010 SAI Transmit Configuration 4 Register (I2S0_TCR4) 32 R/W 0000_0000h
46.3.5/
1153
4002_F014 SAI Transmit Configuration 5 Register (I2S0_TCR5) 32 R/W 0000_0000h
46.3.6/
1154
4002_F020 SAI Transmit Data Register (I2S0_TDR0) 32
W
(always
reads
zero)
0000_0000h
46.3.7/
1155
4002_F040 SAI Transmit FIFO Register (I2S0_TFR0) 32 R 0000_0000h
46.3.8/
1155
4002_F060 SAI Transmit Mask Register (I2S0_TMR) 32 R/W 0000_0000h
46.3.9/
1156
4002_F080 SAI Receive Control Register (I2S0_RCSR) 32 R/W 0000_0000h
46.3.10/
1156
4002_F084 SAI Receive Configuration 1 Register (I2S0_RCR1) 32 R/W 0000_0000h
46.3.11/
1159
4002_F088 SAI Receive Configuration 2 Register (I2S0_RCR2) 32 R/W 0000_0000h
46.3.12/
1160
4002_F08C SAI Receive Configuration 3 Register (I2S0_RCR3) 32 R/W 0000_0000h
46.3.13/
1161
4002_F090 SAI Receive Configuration 4 Register (I2S0_RCR4) 32 R/W 0000_0000h
46.3.14/
1162
4002_F094 SAI Receive Configuration 5 Register (I2S0_RCR5) 32 R/W 0000_0000h
46.3.15/
1163
4002_F0A0 SAI Receive Data Register (I2S0_RDR0) 32 R 0000_0000h
46.3.16/
1164
Table continues on the next page...
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
1146 Freescale Semiconductor, Inc.