Information

46.3.7 SAI Transmit Data Register (I2Sx_TDR)
Addresses: I2S0_TDR0 is 4002_F000h base + 20h offset = 4002_F020h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
W
TDR[31:0]
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2Sx_TDRn field descriptions
Field Description
31–0
TDR[31:0]
Transmit Data Register
The corresponding TCR3[TCE] bit must be set before accessing the channel's transmit data register.
Writes to this register when the transmit FIFO is not full will push the data written into the transmit data
FIFO. Writes to this register when the transmit FIFO is full are ignored.
46.3.8 SAI Transmit FIFO Register (I2Sx_TFR)
The MSB of the read and write pointers is used to distinguish between FIFO full and
empty conditions. If the read and write pointers are identical, then the FIFO is empty. If
the read and write pointers are identical except for the MSB, then the FIFO is full.
Addresses: I2S0_TFR0 is 4002_F000h base + 40h offset = 4002_F040h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 WFP 0 RFP
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2Sx_TFRn field descriptions
Field Description
31–19
Reserved
This read-only field is reserved and always has the value zero.
18–16
WFP
Write FIFO Pointer
FIFO write pointer for transmit data channel.
15–3
Reserved
This read-only field is reserved and always has the value zero.
2–0
RFP
Read FIFO Pointer
FIFO read pointer for transmit data channel.
Chapter 46 Synchronous Audio Interface (SAI)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 1155