Information

I2Sx_RCR2 field descriptions (continued)
Field Description
25
BCP
Bit Clock Polarity
Configures the polarity of the bit clock.
0 Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge.
1 Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.
24
BCD
Bit Clock Direction
Configures the direction of the bit clock.
0 Bit clock is generated externally in Slave mode.
1 Bit clock is generated internally in Master mode.
23–8
Reserved
This read-only field is reserved and always has the value zero.
7–0
DIV
Bit Clock Divide
Divides down the audio master clock to generate the bit clock when configured for an internal bit clock.
The division value is (DIV + 1) * 2.
46.3.13 SAI Receive Configuration 3 Register (I2Sx_RCR3)
This register must not be altered when RCSR[RE] is set.
Addresses: I2S0_RCR3 is 4002_F000h base + 8Ch offset = 4002_F08Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
RCE
0
WDFL
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2Sx_RCR3 field descriptions
Field Description
31–17
Reserved
This read-only field is reserved and always has the value zero.
16
RCE
Receive Channel Enable
Enables a data channel for a receive operation. A channel should be enabled before its FIFO is accessed.
0 Receive data channel is disabled.
1 Receive data channel is enabled.
15–4
Reserved
This read-only field is reserved and always has the value zero.
3–0
WDFL
Word flag configuration
Table continues on the next page...
Chapter 46 Synchronous Audio Interface (SAI)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 1161