Information

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFN 48 EP (7x7) 32-Bit 50 MHz I/O number 29

1161

I2Sx_RCR5 field descriptions (continued)

Field Description

12–8

FBT

First Bit Shifted

Configures the bit index for the first bit received for each word in the frame. If configured for MSB First,

the index of the next bit received is one less than the current bit received. If configured for LSB First, the

index of the next bit received is one more than the current bit received. The value written must be greater

than or equal to the word width when configured for MSB First. The value written must be less than or

equal to 31-word width when configured for LSB First.

7–0

Reserved

This read-only field is reserved and always has the value zero.

46.3.16 SAI Receive Data Register (I2Sx_RDR)

Reading this register introduces one additional peripheral clock wait state on each read.

Addresses: I2S0_RDR0 is 4002_F000h base + A0h offset = 4002_F0A0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RDR[31:0]

Reset

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

I2Sx_RDRn field descriptions

Field Description

31–0

RDR[31:0]

Receive Data Register

The corresponding RCR3[RCE] bit must be set before accessing the channel's receive data register.

Reads from this register when the receive FIFO is not empty will return the data from the top of the

receive FIFO. Reads from this register when the receive FIFO is empty are ignored.

46.3.17 SAI Receive FIFO Register (I2Sx_RFR)

The MSB of the read and write pointers is used to distinguish between FIFO full and

empty conditions. If the read and write pointers are identical, then the FIFO is empty. If

the read and write pointers are identical except for the MSB, then the FIFO is full.

Addresses: I2S0_RFR0 is 4002_F000h base + C0h offset = 4002_F0C0h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 WFP 0 RFP

Reset

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Memory map and register definition

K20 Sub-Family Reference Manual, Rev. 2, Feb 2012

1164 Freescale Semiconductor, Inc.