Information

46.3.20 SAI MCLK Divide Register (I2Sx_MDR)
The MCLK Divide Register (MDR) configures the MCLK divide ratio. Although the
MDR can be changed when the MCLK divider clock is enabled, additional writes to the
MDR are blocked while MCR[DUF] is set. Writes to the MDR when the MCLK divided
clock is disabled do not set MCR[DUF].
Addresses: I2S0_MDR is 4002_F000h base + 104h offset = 4002_F104h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
FRACT DIVIDE
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
I2Sx_MDR field descriptions
Field Description
31–20
Reserved
This read-only field is reserved and always has the value zero.
19–12
FRACT
MCLK Fraction
Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT + 1) / (DIVIDE + 1) ).
FRACT must be set equal or less than the value in the DIVIDE field.
11–0
DIVIDE
MCLK Divide
Sets the MCLK divide ratio such that: MCLK output = MCLK input * ( (FRACT + 1) / (DIVIDE + 1) ).
FRACT must be set equal or less than the value in the DIVIDE field.
Functional description
46.4.1 SAI clocking
The SAI clocks include:
• The audio master clock
• The bit clock
• The bus clock
46.4
Chapter 46 Synchronous Audio Interface (SAI)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 1167