Information

GPIO memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
400F_F00C Port Toggle Output Register (GPIOA_PTOR) 32
W
(always
reads
zero)
0000_0000h
47.2.4/
1181
400F_F010 Port Data Input Register (GPIOA_PDIR) 32 R 0000_0000h
47.2.5/
1182
400F_F014 Port Data Direction Register (GPIOA_PDDR) 32 R/W 0000_0000h
47.2.6/
1183
400F_F040 Port Data Output Register (GPIOB_PDOR) 32 R/W 0000_0000h
47.2.1/
1180
400F_F044 Port Set Output Register (GPIOB_PSOR) 32
W
(always
reads
zero)
0000_0000h
47.2.2/
1180
400F_F048 Port Clear Output Register (GPIOB_PCOR) 32
W
(always
reads
zero)
0000_0000h
47.2.3/
1181
400F_F04C Port Toggle Output Register (GPIOB_PTOR) 32
W
(always
reads
zero)
0000_0000h
47.2.4/
1181
400F_F050 Port Data Input Register (GPIOB_PDIR) 32 R 0000_0000h
47.2.5/
1182
400F_F054 Port Data Direction Register (GPIOB_PDDR) 32 R/W 0000_0000h
47.2.6/
1183
400F_F080 Port Data Output Register (GPIOC_PDOR) 32 R/W 0000_0000h
47.2.1/
1180
400F_F084 Port Set Output Register (GPIOC_PSOR) 32
W
(always
reads
zero)
0000_0000h
47.2.2/
1180
400F_F088 Port Clear Output Register (GPIOC_PCOR) 32
W
(always
reads
zero)
0000_0000h
47.2.3/
1181
400F_F08C Port Toggle Output Register (GPIOC_PTOR) 32
W
(always
reads
zero)
0000_0000h
47.2.4/
1181
400F_F090 Port Data Input Register (GPIOC_PDIR) 32 R 0000_0000h
47.2.5/
1182
400F_F094 Port Data Direction Register (GPIOC_PDDR) 32 R/W 0000_0000h
47.2.6/
1183
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
1178 Freescale Semiconductor, Inc.