Information

Source UART 0 UART 1 UART 2
Transmit data empty x x x
Transmit complete x x x
Idle line x x x
Receive data full x x x
LIN break detect x x x
RxD pin active edge x x x
Initial character detect x — —
The error interrupt combines the following interrupt sources:
Source UART 0 UART 1 UART 2
Receiver overrun x x x
Noise flag x x x
Framing error x x x
Parity error x x x
Transmitter buffer overflow x x x
Receiver buffer underflow x x x
Transmit threshold (ISO7816) x — —
Receiver threshold (ISO7816) x — —
Wait timer (ISO7816) x — —
Character wait timer
(ISO7816)
x — —
Block wait timer (ISO7816) x — —
Guard time violation
(ISO7816)
x — —
The LON status interrupt combines the following interrupt sources:
Source UART 0 UART 1 UART 2
Wbase expire after beta1
time slots (LON)
x — —
Package received (LON) x — —
Package transmitted (LON) x — —
Package cycle time expired
(LON)
x — —
Preamble start (LON) x — —
Transmission fail (LON) x — —
3.9.5 I
2
S configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Chapter 3 Chip Configuration
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 123