Information

3.9.5.2.2 Bit Clock
The I
2
S/SAI transmitter and receiver support asynchronous bit clocks (BCLKs) that can
be generated internally from the audio master clock or supplied externally. The module
also supports the option for synchronous operation between the receiver and transmitter
or between two separate I
2
S/SAI peripherals.
3.9.5.2.3 Bus Clock
The bus clock is used by the control registers and to generate synchronous interrupts and
DMA requests.
3.9.5.2.4 I
2
S/SAI clock generation
Each SAI peripheral can control the input clock selection, pin direction and divide ratio
of one audio master clock.
The MCLK Input Clock Select bit of the MCLK Control Register (MCR[MICS]) selects
the clock input to the I
2
S/SAI module’s MCLK divider.
The following table shows the input clock selection options on this device.
Table 3-63. I2S0 MCLK input clock selection
MCR[MICS] Clock Selection
00 System clock
01 OSC0ERCLK
10 Not supported
11 MCGPLLCLK or MCGFLLCLK
The module's MCLK Divide Register (MDR) configures the MCLK divide ratio.
The module's MCLK Output Enable bit of the MCLK Control Register (MCR[MOE])
controls the direction of the MCLK pin. The pin is the input from the pin when MOE is 0,
and the pin is the output from the clock divider when MOE is 1.
The transmitter and receiver can independently select between the bus clock and the
audio master clock to generate the bit clock. Each module's Clocking Mode field of the
Transmit Configuration 2 Register and Receive Configuration 2 Register (TCR2[MSEL]
and RCR2[MSEL]) selects the master clock.
Chapter 3 Chip Configuration
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 125