Information

Section Number Title Page
20.2 External signal description............................................................................................................................................321
20.3 Memory map/register definition...................................................................................................................................321
20.3.1 Channel Configuration register (DMAMUXx_CHCFGn)..........................................................................322
20.4 Functional description...................................................................................................................................................323
20.4.1 DMA channels with periodic triggering capability......................................................................................323
20.4.2 DMA channels with no triggering capability...............................................................................................325
20.4.3 "Always enabled" DMA sources.................................................................................................................325
20.5 Initialization/application information...........................................................................................................................327
20.5.1 Reset.............................................................................................................................................................327
20.5.2 Enabling and configuring sources................................................................................................................327
Chapter 21
Direct Memory Access Controller (eDMA)
21.1 Introduction...................................................................................................................................................................331
21.1.1 Block diagram..............................................................................................................................................331
21.1.2 Block parts...................................................................................................................................................332
21.1.3 Features........................................................................................................................................................334
21.2 Modes of operation.......................................................................................................................................................335
21.3 Memory map/register definition...................................................................................................................................335
21.3.1 Control Register (DMA_CR).......................................................................................................................340
21.3.2 Error Status Register (DMA_ES)................................................................................................................342
21.3.3 Enable Request Register (DMA_ERQ).......................................................................................................344
21.3.4 Enable Error Interrupt Register (DMA_EEI)...............................................................................................345
21.3.5 Clear Enable Error Interrupt Register (DMA_CEEI)..................................................................................346
21.3.6 Set Enable Error Interrupt Register (DMA_SEEI)......................................................................................347
21.3.7 Clear Enable Request Register (DMA_CERQ)...........................................................................................348
21.3.8 Set Enable Request Register (DMA_SERQ)...............................................................................................349
21.3.9 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................350
21.3.10 Set START Bit Register (DMA_SSRT)......................................................................................................351
21.3.11 Clear Error Register (DMA_CERR)............................................................................................................352
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
14 Freescale Semiconductor, Inc.