Information

5.6 Clock Gating
The clock to each module can be individually gated on and off using the SIM module's
SCGCx registers. These bits are cleared after any reset, which disables the clock to the
corresponding module to conserve power. Prior to initializing a module, set the
corresponding bit in SCGCx register to enable the clock. Before turning off the clock,
make sure to disable the module.
Any bus access to a peripheral that has its clock disabled generates an error termination.
5.7 Module clocks
The following table summarizes the clocks associated with each module.
Table 5-2. Module clocks
Module Bus interface clock Internal clocks I/O interface clocks
Core modules
ARM Cortex-M4 core System clock Core clock —
NVIC System clock — —
DAP System clock — —
ITM System clock — —
cJTAG, JTAGC — — JTAG_CLK
System modules
DMA System clock — —
DMA Mux Bus clock — —
Port control Bus clock LPO —
Crossbar Switch System clock — —
Peripheral bridges System clock Bus clock, Flash clock —
LLWU, PMC, SIM, RCM Flash clock LPO —
Mode controller Flash clock — —
MCM System clock — —
EWM Bus clock LPO —
Watchdog timer Bus clock LPO —
Clocks
Table continues on the next page...
Clock Gating
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
146 Freescale Semiconductor, Inc.