Information

10.2.4 Signal multiplexing constraints
1. A given peripheral function must be assigned to a maximum of one package pin. Do
not program the same function to more than one pin.
2. To ensure the best signal timing for a given peripheral's interface, choose the pins in
closest proximity to each other.
10.3 Pinout
10.3.1 K20 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
48
LQF
P-
QFN
32
QFN
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
1 1 VDD VDD VDD
2 2 VSS VSS VSS
3 3 USB0_DP USB0_DP USB0_DP
4 4 USB0_DM USB0_DM USB0_DM
5 5 VOUT33 VOUT33 VOUT33
6 6 VREGIN VREGIN VREGIN
7 — ADC0_DP0 ADC0_DP0 ADC0_DP0
8 — ADC0_DM0 ADC0_DM0 ADC0_DM0
9 7 VDDA VDDA VDDA
10 — VREFH VREFH VREFH
11 — VREFL VREFL VREFL
12 8 VSSA VSSA VSSA
13 — VREF_OUT/
CMP1_IN5/
CMP0_IN5
VREF_OUT/
CMP1_IN5/
CMP0_IN5
VREF_OUT/
CMP1_IN5/
CMP0_IN5
14 9 XTAL32 XTAL32 XTAL32
15 10 EXTAL32 EXTAL32 EXTAL32
16 11 VBAT VBAT VBAT
17 12 PTA0 JTAG_TCL
K/
SWD_CLK/
EZP_CLK
TSI0_CH1 PTA0 UART0_CT
S_b/
UART0_CO
L_b
FTM0_CH5 JTAG_TCL
K/
SWD_CLK
EZP_CLK
Chapter 10 Signal Multiplexing and Signal Descriptions
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 193