Information
48
LQF
P-
QFN
32
QFN
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
18 13 PTA1 JTAG_TDI/
EZP_DI
TSI0_CH2 PTA1 UART0_RX FTM0_CH6 JTAG_TDI EZP_DI
19 14 PTA2 JTAG_TDO/
TRACE_SW
O/EZP_DO
TSI0_CH3 PTA2 UART0_TX FTM0_CH7 JTAG_TDO/
TRACE_SW
O
EZP_DO
20 15 PTA3 JTAG_TMS/
SWD_DIO
TSI0_CH4 PTA3 UART0_RT
S_b
FTM0_CH0 JTAG_TMS/
SWD_DIO
21 16 PTA4/
LLWU_P3
NMI_b/
EZP_CS_b
TSI0_CH5 PTA4/
LLWU_P3
FTM0_CH1 NMI_b EZP_CS_b
22 — VDD VDD VDD
23 — VSS VSS VSS
24 17 PTA18 EXTAL0 EXTAL0 PTA18 FTM0_FLT2 FTM_CLKIN
0
25 18 PTA19 XTAL0 XTAL0 PTA19 FTM1_FLT0 FTM_CLKIN
1
LPTMR0_A
LT1
26 19 RESET_b RESET_b RESET_b
27 20 PTB0/
LLWU_P5
ADC0_SE8/
TSI0_CH0
ADC0_SE8/
TSI0_CH0
PTB0/
LLWU_P5
I2C0_SCL FTM1_CH0 FTM1_QD_
PHA
28 21 PTB1 ADC0_SE9/
TSI0_CH6
ADC0_SE9/
TSI0_CH6
PTB1 I2C0_SDA FTM1_CH1 FTM1_QD_
PHB
29 — PTB2 ADC0_SE1
2/TSI0_CH7
ADC0_SE1
2/TSI0_CH7
PTB2 I2C0_SCL UART0_RT
S_b
FTM0_FLT3
30 — PTB3 ADC0_SE1
3/TSI0_CH8
ADC0_SE1
3/TSI0_CH8
PTB3 I2C0_SDA UART0_CT
S_b/
UART0_CO
L_b
FTM0_FLT0
31 — PTB16 TSI0_CH9 TSI0_CH9 PTB16 UART0_RX EWM_IN
32 — PTB17 TSI0_CH10 TSI0_CH10 PTB17 UART0_TX EWM_OUT
_b
33 — PTC0 ADC0_SE1
4/
TSI0_CH13
ADC0_SE1
4/
TSI0_CH13
PTC0 SPI0_PCS4 PDB0_EXT
RG
34 22 PTC1/
LLWU_P6
ADC0_SE1
5/
TSI0_CH14
ADC0_SE1
5/
TSI0_CH14
PTC1/
LLWU_P6
SPI0_PCS3 UART1_RT
S_b
FTM0_CH0 I2S0_TXD0
35 23 PTC2 ADC0_SE4
b/
CMP1_IN0/
TSI0_CH15
ADC0_SE4
b/
CMP1_IN0/
TSI0_CH15
PTC2 SPI0_PCS2 UART1_CT
S_b
FTM0_CH1 I2S0_TX_F
S
36 24 PTC3/
LLWU_P7
CMP1_IN1 CMP1_IN1 PTC3/
LLWU_P7
SPI0_PCS1 UART1_RX FTM0_CH2 I2S0_TX_B
CLK
37 25 PTC4/
LLWU_P8
DISABLED PTC4/
LLWU_P8
SPI0_PCS0 UART1_TX FTM0_CH3 CMP1_OUT
38 26 PTC5/
LLWU_P9
DISABLED PTC5/
LLWU_P9
SPI0_SCK LPTMR0_A
LT2
I2S0_RXD0 CMP0_OUT
39 27 PTC6/
LLWU_P10
CMP0_IN0 CMP0_IN0 PTC6/
LLWU_P10
SPI0_SOUT PDB0_EXT
RG
I2S0_RX_B
CLK
I2S0_MCLK
Pinout
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
194 Freescale Semiconductor, Inc.