Information

48
LQF
P-
QFN
32
QFN
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
40 28 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_SIN USB_SOF_
OUT
I2S0_RX_F
S
41 — PTD0/
LLWU_P12
DISABLED PTD0/
LLWU_P12
SPI0_PCS0 UART2_RT
S_b
42 — PTD1 ADC0_SE5
b
ADC0_SE5
b
PTD1 SPI0_SCK UART2_CT
S_b
43 — PTD2/
LLWU_P13
DISABLED PTD2/
LLWU_P13
SPI0_SOUT UART2_RX
44 — PTD3 DISABLED PTD3 SPI0_SIN UART2_TX
45 29 PTD4/
LLWU_P14
DISABLED PTD4/
LLWU_P14
SPI0_PCS1 UART0_RT
S_b
FTM0_CH4 EWM_IN
46 30 PTD5 ADC0_SE6
b
ADC0_SE6
b
PTD5 SPI0_PCS2 UART0_CT
S_b/
UART0_CO
L_b
FTM0_CH5 EWM_OUT
_b
47 31 PTD6/
LLWU_P15
ADC0_SE7
b
ADC0_SE7
b
PTD6/
LLWU_P15
SPI0_PCS3 UART0_RX FTM0_CH6 FTM0_FLT0
48 32 PTD7 DISABLED PTD7 CMT_IRO UART0_TX FTM0_CH7 FTM0_FLT1
10.3.2 K20 Pinouts
The below figure shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
Chapter 10 Signal Multiplexing and Signal Descriptions
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 195