Information

10.4.1 Core Modules
Table 10-2. JTAG Signal Descriptions
Chip signal name Module signal
name
Description I/O
JTAG_TMS JTAG_TMS/
SWD_DIO
JTAG Test Mode Selection I/O
JTAG_TCLK JTAG_TCLK/
SWD_CLK
JTAG Test Clock I
JTAG_TDI JTAG_TDI JTAG Test Data Input I
JTAG_TDO JTAG_TDO/
TRACE_SWO
JTAG Test Data Output O
JTAG_TRST JTAG_TRST_b JTAG Reset I
Table 10-3. SWD Signal Descriptions
Chip signal name Module signal
name
Description I/O
SWD_DIO JTAG_TMS/
SWD_DIO
Serial Wire Data I/O
SWD_CLK JTAG_TCLK/
SWD_CLK
Serial Wire Clock I
Table 10-4. TPIU Signal Descriptions
Chip signal name Module signal
name
Description I/O
TRACE_SWO JTAG_TDO/
TRACE_SWO
Trace output data from the ARM CoreSight debug block over a
single pin
O
10.4.2 System Modules
Table 10-5. System Signal Descriptions
Chip signal name Module signal
name
Description I/O
NMI — Non-maskable interrupt
NOTE: Driving the NMI signal low forces a non-maskable
interrupt, if the NMI function is selected on the
corresponding pin.
I
RESET — Reset bi-directional signal I/O
VDD — MCU power I
VSS — MCU ground I
Chapter 10 Signal Multiplexing and Signal Descriptions
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 197