Information

10.4.5 Analog
Table 10-10. ADC 0 Signal Descriptions
Chip signal name Module signal
name
Description I/O
ADC0_DPn DADP[3:0] Differential analog channel inputs I
ADC0_DMn DADM[3:0] Differential analog channel inputs I
ADC0_SEn AD[23:4] Single-ended analog channel inputs I
VREFH V
REFSH
Voltage reference select high I
VREFL V
REFSL
Voltage reference select low I
VDDA V
DDA
Analog power supply I
VSSA V
SSA
Analog ground I
Table 10-11. CMP 0 Signal Descriptions
Chip signal name Module signal
name
Description I/O
CMP0_IN[5:0] IN[5:0] Analog voltage inputs I
CMP0_OUT CMPO Comparator output O
Table 10-12. CMP 1 Signal Descriptions
Chip signal name Module signal
name
Description I/O
CMP1_IN[5:0] IN[5:0] Analog voltage inputs I
CMP1_OUT CMPO Comparator output O
Table 10-13. VREF Signal Descriptions
Chip signal name Module signal
name
Description I/O
VREF_OUT VREF_OUT Internally-generated Voltage Reference output O
10.4.6 Communication Interfaces
Table 10-14. USB FS OTG Signal Descriptions
Chip signal name Module signal
name
Description I/O
USB0_DM usb_dm USB D- analog data signal on the USB bus. I/O
USB0_DP usb_dp USB D+ analog data signal on the USB bus. I/O
USB_CLKIN — Alternate USB clock input I
Chapter 10 Signal Multiplexing and Signal Descriptions
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 199