Information

SIM_SOPT2 field descriptions
Field Description
31–30
Reserved
This read-only field is reserved and always has the value zero.
29–28
Reserved
This read-only field is reserved and always has the value zero.
27–22
Reserved
This read-only field is reserved and always has the value zero.
21–19
Reserved
This read-only field is reserved and always has the value zero.
18
USBSRC
USB clock source select
Selects the clock source for the USB 48 MHz clock.
0 External bypass clock (USB_CLKIN).
1 MCGPLLCLK/MCGFLLCLK clock divided by the USB fractional divider. See the
SIM_CLKDIV2[USBFRAC, USBDIV] descriptions.
17
Reserved
This read-only field is reserved and always has the value zero.
16
PLLFLLSEL
PLL/FLL clock select
Selects the MCGPLLCLK or MCGFLLCLK clock for various peripheral clocking options.
0 MCGFLLCLK clock
1 MCGPLLCLK clock
15–13
Reserved
This read-only field is reserved and always has the value zero.
12
TRACECLKSEL
Debug trace clock select
Selects the core/system clock or MCG output clock (MCGOUTCLK) as the trace clock source.
0 MCGOUTCLK
1 Core/system clock
11
PTD7PAD
PTD7 pad drive strength
Controls the output drive strength of the PTD7 pin by selecting either one or two pads to drive it.
0 Single-pad drive strength for PTD7.
1 Double pad drive strength for PTD7.
10
Reserved
This read-only field is reserved and always has the value zero.
9–8
Reserved
This read-only field is reserved and always has the value zero.
7–5
CLKOUTSEL
CLKOUT select
Selects the clock to output on the CLKOUT pin.
000 Reserved
001 Reserved
010 Flash clock
Table continues on the next page...
Chapter 12 System Integration Module (SIM)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 225