Information

12.2.8 System Clock Gating Control Register 4 (SIM_SCGC4)
Address: SIM_SCGC4 is 4004_7000h base + 1034h offset = 4004_8034h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
1 0
VREF
CMP
USBOTG
0
W
Reset
1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 0
UART2 UART1 UART0
0 0
I2C0
1 0
CMT
EWM
0
W
Reset
0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0
SIM_SCGC4 field descriptions
Field Description
31–28
Reserved
This read-only field is reserved and always has the value one.
27–21
Reserved
This read-only field is reserved and always has the value zero.
20
VREF
VREF Clock Gate Control
This bit controls the clock gate to the VREF module.
0 Clock disabled
1 Clock enabled
19
CMP
Comparator Clock Gate Control
This bit controls the clock gate to the comparator module.
0 Clock disabled
1 Clock enabled
18
USBOTG
USB Clock Gate Control
This bit controls the clock gate to the USB module.
0 Clock disabled
1 Clock enabled
17–14
Reserved
This read-only field is reserved and always has the value zero.
13
Reserved
This read-only field is reserved and always has the value zero.
Table continues on the next page...
Chapter 12 System Integration Module (SIM)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 235