Information

SIM_CLKDIV1 field descriptions (continued)
Field Description
1101 Divide-by-14.
1110 Divide-by-15.
1111 Divide-by-16.
27–24
OUTDIV2
Clock 2 output divider value
This field sets the divide value for the peripheral clock. At the end of reset, it is loaded with either 0000 or
0111 depending on FTFL_FOPT[LPBOOT].
0000 Divide-by-1.
0001 Divide-by-2.
0010 Divide-by-3.
0011 Divide-by-4.
0100 Divide-by-5.
0101 Divide-by-6.
0110 Divide-by-7.
0111 Divide-by-8.
1000 Divide-by-9.
1001 Divide-by-10.
1010 Divide-by-11.
1011 Divide-by-12.
1100 Divide-by-13.
1101 Divide-by-14.
1110 Divide-by-15.
1111 Divide-by-16.
23–20
Reserved
This read-only field is reserved and always has the value zero.
19–16
OUTDIV4
Clock 4 output divider value
This field sets the divide value for the flash clock. At the end of reset, it is loaded with either 0001 or 1111
depending on FTFL_FOPT[LPBOOT].
0000 Divide-by-1.
0001 Divide-by-2.
0010 Divide-by-3.
0011 Divide-by-4.
0100 Divide-by-5.
0101 Divide-by-6.
0110 Divide-by-7.
0111 Divide-by-8.
1000 Divide-by-9.
1001 Divide-by-10.
1010 Divide-by-11.
1011 Divide-by-12.
1100 Divide-by-13.
1101 Divide-by-14.
1110 Divide-by-15.
1111 Divide-by-16.
Table continues on the next page...
Chapter 12 System Integration Module (SIM)
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 243