Information

Section Number Title Page
32.4 ANMUX key features...................................................................................................................................................633
32.5 CMP, DAC and ANMUX diagram...............................................................................................................................633
32.6 CMP block diagram......................................................................................................................................................634
32.7 Memory map/register definitions..................................................................................................................................636
32.7.1 CMP Control Register 0 (CMPx_CR0).......................................................................................................637
32.7.2 CMP Control Register 1 (CMPx_CR1).......................................................................................................638
32.7.3 CMP Filter Period Register (CMPx_FPR)...................................................................................................639
32.7.4 CMP Status and Control Register (CMPx_SCR).........................................................................................639
32.7.5 DAC Control Register (CMPx_DACCR)....................................................................................................641
32.7.6 MUX Control Register (CMPx_MUXCR)..................................................................................................641
32.8 CMP functional description..........................................................................................................................................642
32.8.1 CMP functional modes.................................................................................................................................642
32.8.2 Power modes................................................................................................................................................652
32.8.3 Startup and operation...................................................................................................................................653
32.8.4 Low-pass filter.............................................................................................................................................654
32.9 CMP interrupts..............................................................................................................................................................656
32.10 CMP DMA support.......................................................................................................................................................656
32.11 Digital-to-analog converter block diagram...................................................................................................................657
32.12 DAC functional description..........................................................................................................................................657
32.12.1 Voltage reference source select....................................................................................................................657
32.13 DAC resets....................................................................................................................................................................658
32.14 DAC clocks...................................................................................................................................................................658
32.15 DAC interrupts..............................................................................................................................................................658
Chapter 33
Voltage Reference (VREFV1)
33.1 Introduction...................................................................................................................................................................659
33.1.1 Overview......................................................................................................................................................660
33.1.2 Features........................................................................................................................................................660
33.1.3 Modes of Operation.....................................................................................................................................661
K20 Sub-Family Reference Manual, Rev. 2, Feb 2012
Freescale Semiconductor, Inc. 25